公开(公告)号：US10763841B2

公开(公告)日：2020-09-01

申请号：US16535557

申请日：2019-08-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huanzhang Huang ,  Amit Rane

IPC: G06F13/38 ,  H03K17/00 ,  H03K19/003 ,  H03K17/56

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

公开(公告)号：US10484042B2

公开(公告)日：2019-11-19

申请号：US16118621

申请日：2018-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Amit Rane

IPC: H04B1/58 ,  H04L25/02 ,  H03K19/0175 ,  H03F3/45

Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.

公开(公告)号：US10038577B2

公开(公告)日：2018-07-31

申请号：US15394292

申请日：2016-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit Rane ,  Roland Ribeiro ,  Leung Kin Chiu

IPC: H03H7/40 ,  H04L25/03

CPC classification number: H04L25/03949 ,  H04L25/03038 ,  H04L2025/03745

Abstract: One example includes a system that is comprised of an equalizer, a counter, and a controller. The equalizer equalizes an incoming signal and provide an equalized output signal over a plurality of time intervals according to a given equalizer setting thereof. The counter provides a count value to represent to a number of times that the equalized output signal crosses each of a plurality of thresholds over the plurality of time intervals. The controller evaluates the count value for each of the plurality of thresholds at each of a plurality of equalizer settings and configures the equalizer setting based on the evaluation of the count values for each of the equalizer settings.

公开(公告)号：US10972319B2

公开(公告)日：2021-04-06

申请号：US16128605

申请日：2018-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit Rane

IPC: H04L25/03

Abstract: An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.

公开(公告)号：US10804956B2

公开(公告)日：2020-10-13

申请号：US16599377

申请日：2019-10-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Amit Rane

IPC: H04B1/58 ,  H04L25/02 ,  H03K19/0175 ,  H03F3/45

Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.

公开(公告)号：US20190312759A1

公开(公告)日：2019-10-10

申请号：US15960532

申请日：2018-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dongwei Chen ,  Amit Rane

IPC: H04L25/49 ,  H04L25/03

Abstract: A signal path linearizer for PAM4 SerDes communications compensates (including pre-compensates) for signal path nonlinearities. The linearizer can be configured with first and second differential gm stages, the first differential gm stage to provide a DC gain, and the second differential gm stage to introduce a defined nonlinear adjustment in DC gain by adding to or subtracting from the DC gain of the first differential gm stage. The differential gm stages can be configured to generate a compensated PAM4 signal with the combined DC gain providing a nonlinear wideband gain adjustment to compensate for nonlinearities in the PAM4 signal path. Compensation range can be increased by selective degeneration, and the compensation region can be shifted by selectively introducing input offset(s).

公开(公告)号：US10128804B2

公开(公告)日：2018-11-13

申请号：US15394931

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit Rane ,  Dongwei Chen

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/30 ,  H03F1/32

Abstract: An equalizer, in at least some embodiments, comprises an amplifier configured to produce an amplified voltage signal that is a function of an ambient temperature affecting the equalizer. The equalizer also includes a linear equalizer stage coupled to the amplifier and comprising a transistor having a resistance controlled by the amplified voltage signal. The linear equalizer stage is configured to produce a voltage output signal having a gain that is dependent on the transistor resistance and on a frequency of the amplified voltage signal.

公开(公告)号：US11539555B2

公开(公告)日：2022-12-27

申请号：US17095869

申请日：2020-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Ashwin Kottilvalappil Vijayan ,  Amit Rane ,  Ashkan Roshan Zamir

IPC: H04L25/03 ,  H03F3/45 ,  H03H17/06 ,  G11C27/02 ,  G05F1/56 ,  H03H11/04 ,  H03F3/183

Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

公开(公告)号：US11356086B2

公开(公告)日：2022-06-07

申请号：US17163894

申请日：2021-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huanzhang Huang ,  Amit Rane

IPC: G06F13/38 ,  H03K17/00 ,  H03K19/003 ,  H03K17/56

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

公开(公告)号：US10979252B1

公开(公告)日：2021-04-13

申请号：US16892943

申请日：2020-06-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yanli Fan ,  Amit Rane

IPC: H04L25/02 ,  H03G3/30 ,  H03F3/72

Abstract: Aspects of the disclosure provide for a circuit comprising a transmitter. In at least some examples, the transmitter is configured to receive an input signal and a loss of signal indication signal. The transmitter is further configured to dynamically modify processing of the input signal based on the loss of signal indication signal. The transmitter modifies processing of the input signal based on the loss of signal indication signal by processing the input signal via a limiting driver signal path to generate an output signal when the loss of signal indication signal has a first value and processing the input signal via a linear driver signal path to generate the output signal when the loss of signal indication signal has a second value.