公开(公告)号：US20180269272A1

公开(公告)日：2018-09-20

申请号：US15462741

申请日：2017-03-17

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Barry Jon Male ,  Robert Alan Neidorff

IPC: H01L49/02 ,  H01L23/66 ,  H01L23/495

CPC classification number: H01L28/60 ,  H01L23/49575 ,  H01L23/66 ,  H01L2223/6611

Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

公开(公告)号：US20180190628A1

公开(公告)日：2018-07-05

申请号：US15395584

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Barry Jon Male ,  Benjamin Cook ,  Robert Alan Neidorff ,  Steve Kummerl

IPC: H01L25/16 ,  H01L31/02 ,  H01L31/167 ,  H01L49/02 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L25/167 ,  H01F38/14 ,  H01L23/315 ,  H01L23/49 ,  H01L23/49575 ,  H01L24/08 ,  H01L24/48 ,  H01L24/85 ,  H01L28/10 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/101 ,  H01L31/103 ,  H01L31/1105 ,  H01L31/167 ,  H01L33/00 ,  H01L33/62 ,  H01L2224/08113 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2924/12041 ,  H01L2924/12043 ,  H04B10/803

Abstract: Disclosed examples include integrated circuits with a leadframe structure, a first circuit structure including a light source configured to generate a light signal along an optical path, a second circuit structure including a light sensor facing the optical path to receive the light signal, and a molded package structure enclosing portions of the leadframe structure, the molded package structure having a cavity defined by an interior surface of the molded package structure, the optical path extending in the cavity between the first and second circuit structures.

公开(公告)号：US12237247B2

公开(公告)日：2025-02-25

申请号：US18527457

申请日：2023-12-04

Applicant: Texas Instruments Incorporated

Inventor： Barry Jon Male ,  Paul Merle Emerson ,  Sandeep Shylaja Krishnan

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.

公开(公告)号：US11884538B2

公开(公告)日：2024-01-30

申请号：US17487203

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marco Corsi ,  Barry Jon Male

IPC: B81B7/02 ,  B81B7/00 ,  B81C1/00

CPC classification number: B81B7/008 ,  B81B7/007 ,  B81B7/02 ,  B81C1/00238 ,  B81B2201/0278

Abstract: A sensor device includes a first and second Micro-Electro-Mechanical (MEM) structures. The first MEM structure includes a first heating element on a first layer of the first MEM structure. The first heating element includes an input adapted to receive an input signal. The first MEM structure also includes a first temperature sensing element on a second layer of the first MEM structure. The second MEM structure includes a second heating element on a first layer of the second MEM structure and a second temperature sensing element on a second layer of the second MEM structure. An output circuit has a first input coupled to the first temperature sensing element and a second input coupled to the second temperature sensing element.

公开(公告)号：US11495522B2

公开(公告)日：2022-11-08

申请号：US17120941

申请日：2020-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Barry Jon Male ,  Marco Corsi

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/532

Abstract: In examples, an electronic device comprises a printed circuit board (PCB), an orifice extending through the PCB, and a semiconductor die suspended above the orifice by aluminum bond wires. The semiconductor die is vertically aligned with the orifice and the bond wires coupled to the PCB.

公开(公告)号：US20220208657A1

公开(公告)日：2022-06-30

申请号：US17698855

申请日：2022-03-18

Applicant: Texas Instruments Incorporated

Inventor： Barry Jon Male ,  Paul Merle Emerson ,  Sandeep Shylaja Krishnan

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

公开(公告)号：US11296016B2

公开(公告)日：2022-04-05

申请号：US15808537

申请日：2017-11-09

Applicant: Texas Instruments Incorporated

Inventor： Robert Allan Neidorff ,  Benjamin Cook ,  Steven Alfred Kummerl ,  Barry Jon Male ,  Peter Smeys

IPC: H01L23/495 ,  H01L23/485 ,  H01L23/31 ,  B81C1/00

Abstract: Semiconductor devices and methods and apparatus to produce such semiconductor devices are disclosed. An integrated circuit package includes a lead frame including a die attach pad and a plurality of leads; a die including a MEMs region defined by a plurality of trenches, the die electrically connected to the plurality of leads; and a mold compound covering portions of the die, the mold compound defining a cavity between a surface of the die and a surface of the mold compound, wherein the mold compound defines a vent.

公开(公告)号：US20220102609A1

公开(公告)日：2022-03-31

申请号：US17550067

申请日：2021-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Barry Jon Male ,  Henry Litzmann Edwards

IPC: H01L35/30 ,  H01L35/32 ,  H03K17/605 ,  H03K17/567 ,  H03K17/689 ,  H01L27/16

Abstract: A system on an integrated circuit (IC) chip includes an input terminal and a return terminal, a heater, a thermopile, and a switch device. The heater is coupled between the input terminal and the return terminal. The thermopile is spaced apart from the heater by a galvanic isolation region. The switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip.

公开(公告)号：US10529796B2

公开(公告)日：2020-01-07

申请号：US16178352

申请日：2018-11-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Barry Jon Male ,  Robert Alan Neidorff

IPC: H01L49/02 ,  H01L23/66 ,  H01L23/495

Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

公开(公告)号：US20190006338A1

公开(公告)日：2019-01-03

申请号：US16126577

申请日：2018-09-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Barry Jon Male ,  Benjamin Stassen Cook ,  Robert Alan Neidorff ,  Steve Kummerl

IPC: H01L25/16 ,  H04B10/80 ,  H01L31/103 ,  H01L23/31 ,  H01L23/49 ,  H01L23/495 ,  H01L23/00 ,  H01L33/62 ,  H01L33/00 ,  H01L31/167 ,  H01L31/11 ,  H01F38/14 ,  H01L31/101 ,  H01L31/0203 ,  H01L31/02 ,  H01L49/02

Abstract: In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.