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公开(公告)号：US20170212214A1
公开(公告)日：2017-07-27
申请号：US15004443
申请日：2016-01-22
Applicant: Texas Instruments Incorporated
Inventor： Sriram Murali , Karthik Subburaj , Karthik Ramasubramanian
IPC: G01S7/35
CPC classification number: G01S7/352 , G01S7/4021 , G01S13/931 , G01S2007/358 , G01S2007/406
Abstract: A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.
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公开(公告)号：US20150015438A1
公开(公告)日：2015-01-15
申请号：US14037052
申请日：2013-09-25
Applicant: Texas Instruments Incorporated
Inventor： Karthik SUBBURAJ , Karthik Ramasubramanian , Jawaharlal Tangudu
IPC: G01S19/24
CPC classification number: G01S19/24 , G01S19/246 , G01S19/25
Abstract: A method of acquiring a satellite signal in a GNSS receiver includes multiplying a received signal with a hypothesized doppler frequency signal to generate a frequency shifted signal. A PN code sequence signal is multiplied with the frequency shifted signal to generate a PN wiped signal. A windowing function signal is multiplied with the PN wiped signal to generate a windowed signal. The windowed signal is integrated coherently for a first predefined time to generate a coherent accumulated data.
Abstract translation: 在GNSS接收机中获取卫星信号的方法包括将接收信号与假设的多普勒频率信号相乘以产生频移信号。 PN码序列信号与频移信号相乘以产生PN擦除信号。 加窗功能信号与PN擦除信号相乘以产生加窗信号。 窗口信号被相干地整合在第一预定义时间以产生相干累积数据。
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公开(公告)号：US08897401B2
公开(公告)日：2014-11-25
申请号：US14309303
申请日：2014-06-19
Applicant: Texas Instruments Incorporated
Inventor： Bijoy Bhukania , Jawaharlal Tangudu , Karthik Ramasubramanian
CPC classification number: H03G3/3036 , H03M1/185 , H04B1/1036 , H04B17/309 , H04B17/345 , H04L27/08
Abstract: Automatic gain control in a receiver. A method for controlling operating range of an analog-to-digital converter (ADC) by an automatic gain control circuit includes estimating a peak-to-average ratio corresponding to an analog signal from digital samples of the analog signal. The method includes determining a peak value corresponding to the analog signal based on the peak-to-average ratio. Further, the method includes maintaining magnitude of the analog signal at an input of the ADC and gain of the receiver based on the peak value.
Abstract translation: 接收机自动增益控制。 用于通过自动增益控制电路控制模数转换器（ADC）的操作范围的方法包括从模拟信号的数字样本估计对应于模拟信号的峰均比。 该方法包括基于峰均比来确定与模拟信号相对应的峰值。 此外，该方法包括基于峰值来维持ADC的输入处的模拟信号的幅度和接收机的增益。
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公开(公告)号：US20140036978A1
公开(公告)日：2014-02-06
申请号：US14047204
申请日：2013-10-07
Applicant: Texas Instruments Incorporated
Inventor： Bijoy Bhukania , Jawaharlal Tangudu , Karthik Ramasubramanian
IPC: H04B17/00
CPC classification number: H03G3/3036 , H03M1/185 , H04B1/1036 , H04B17/309 , H04B17/345 , H04L27/08
Abstract: Automatic gain control in a receiver. A method for controlling operating range of an analog-to-digital converter (ADC) by an automatic gain control circuit includes estimating a peak-to-average ratio corresponding to an analog signal from digital samples of the analog signal. The method includes determining a peak value corresponding to the analog signal based on the peak-to-average ratio. Further, the method includes maintaining magnitude of the analog signal at an input of the ADC and gain of the receiver based on the peak value.
Abstract translation: 接收机自动增益控制。 用于通过自动增益控制电路控制模数转换器（ADC）的操作范围的方法包括从模拟信号的数字样本估计对应于模拟信号的峰均比。 该方法包括基于峰均比来确定与模拟信号相对应的峰值。 此外，该方法包括基于峰值来维持ADC的输入处的模拟信号的幅度和接收机的增益。
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公开(公告)号：US20250111007A1
公开(公告)日：2025-04-03
申请号：US18901256
申请日：2024-09-30
Applicant: Texas Instruments Incorporated
Inventor： Kanish B , Karthik Subburaj , Karthik Ramasubramanian , Anushree Pendharkar , Kameswaran Vengattaramane , Atman Kar
Abstract: In described examples, an integrated circuit (IC) includes a fast Fourier transform (FFT) engine, a first memory, a second memory, a conjugate symmetric combiner (CSC), and a control circuit coupled to control them. The first and second memories are coupled to the FFT engine, and the CSC is coupled to the first and second memories and the FFT engine. The FFT engine receives and processes a first stream of samples to generate a second stream of samples. In a first phase, the FFT engine provides a first portion of the second stream of samples to the first memory. In a second phase, the FFT engine provides a second portion of the second stream of samples to the second memory, the first memory provides the first portion of the second stream of samples to the CSC, and the CSC responsively generates a third stream of samples.
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Patent Agency Ranking
公开(公告)号：US12228680B2
公开(公告)日：2025-02-18
申请号：US17862738
申请日：2022-07-12
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Shankar Narayanamoorthy , Karthik Ramasubramanian , Anand Gadiyar , Dheeraj Kumar Shetty , Shailesh Joshi
IPC: G01S7/40
Abstract: Methods, apparatus, systems and articles of manufacture to compensate radar system calibration are disclosed. A radio-frequency (RF) subsystem having a transmit channel, a receive channel, and a loopback path comprising at least a portion of the transmit channel and at least a portion of the receive channel, a loopback measurer to measure a first loopback response of the RF subsystem for a first calibration configuration of the RF subsystem, and to measure a second loopback response of the RF subsystem for a second calibration configuration of the RF subsystem, and a compensator to adjust at least one of a transmit programmable shifter or a digital front end based on a difference between the first loopback response and the second loopback response to compensate for a loopback response change when the RF subsystem is changed from the first calibration configuration to the second calibration configuration.
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公开(公告)号：US20250020771A1
公开(公告)日：2025-01-16
申请号：US18904286
申请日：2024-10-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Pankaj Gupta , Karthik Ramasubramanian
Abstract: Devices, e.g., hardware accelerators, and systems are operable to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.
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公开(公告)号：US11747436B2
公开(公告)日：2023-09-05
申请号：US17020931
申请日：2020-09-15
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Karthik Ramasubramanian , Sriram Murali , Sreekiran Samala , Krishnanshu Dandu
IPC: G01S7/292 , G01S13/88 , G01S13/00 , G01S7/35 , G01S13/34 , G01S7/03 , G01S7/02 , G01S7/41 , G01S13/04
CPC classification number: G01S7/292 , G01S7/023 , G01S7/038 , G01S7/354 , G01S7/414 , G01S13/003 , G01S13/343 , G01S13/88 , G01S7/356 , G01S7/358 , G01S13/04
Abstract: A noise-mitigated continuous-wave frequency-modulated radar includes, for example, a transmitter for generating a radar signal, a receiver for receiving a reflected radar signal and comprising a mixer for generating a baseband signal in response to the received radar signal and in response to a local oscillator (LO) signal, and a signal shifter coupled to at least one of the transmitter, LO input of the mixer in the receiver and the baseband signal generated by the mixer. The impact of amplitude noise or phase noise associated with interferers, namely, for example, strong reflections from nearby objects, and electromagnetic coupling from transmit antenna to receive antenna, on the detection of other surrounding objects is reduced by configuring the signal shifter in response to an interferer frequency and phase offset.
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公开(公告)号：US11579242B2
公开(公告)日：2023-02-14
申请号：US16442152
申请日：2019-06-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian , Indu Prathapan , Raghu Ganesan , Pankaj Gupta
Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.
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公开(公告)号：US11221397B2
公开(公告)日：2022-01-11
申请号：US16376515
申请日：2019-04-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Pankaj Gupta , Karthik Ramasubramanian
Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.
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