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公开(公告)号：US12196847B2
公开(公告)日：2025-01-14
申请号：US16121689
申请日：2018-09-05
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Rao , Karthik Subburaj , Brian Ginsburg , Karthik Ramasubramanian , Jawaharlal Tangudu , Sachin Bharadwaj
IPC: G01S13/58 , G01S7/35 , G01S13/34 , G01S13/931
Abstract: The disclosure provides a radar apparatus for estimating a range of an obstacle. The radar apparatus includes a local oscillator that generates a first ramp segment and a second ramp segment. The first ramp segment and the second ramp segment each includes a start frequency, a first frequency and a second frequency. The first frequency of the second ramp segment is equal to or greater than the second frequency of the first ramp segment when a slope of the first ramp segment and a slope of the second ramp segment are equal and positive. The first frequency of the second ramp segment is equal to or less than the second frequency of the first ramp segment when the slope of the first ramp segment and the slope of the second ramp segment are equal and negative.
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公开(公告)号：US20240272275A1
公开(公告)日：2024-08-15
申请号：US18222047
申请日：2023-07-14
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Rao , Anil Mani , Karthik Ramasubramanian
IPC: G01S7/35
CPC classification number: G01S7/352
Abstract: A radar system may include a radar sensor circuit, a compression estimation circuit, a compression circuit, and a data storage circuit. The radar sensor circuit may receive a set of sensor data associated with a radar chirp signal. The radar sensor circuit may generate a set of range data associated with the set of sensor data, which may include first range data for a first range bin and second range data for a second range bin. The compression estimation circuit may determine a first compression ratio for the first range data and a second compression ratio for the second range data. The compression circuit may compress the first and second range data based on the first and second compression ratios respectively. The compressed first and second range data may be stored at the data storage circuit.
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公开(公告)号：US11782148B2
公开(公告)日：2023-10-10
申请号：US16363719
申请日：2019-03-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Karthik Subburaj , Sandeep Rao , Sriram Murali , Karthik Ramasubramanian
CPC classification number: G01S13/584 , G01S7/352 , G01S7/356 , G01S13/343 , G01S13/345
Abstract: Aspects of the present disclosure provide for a radar system including a radar IC including a timing engine, a local oscillator, and a modulator. The timing engine is configured to generate one or more chirp control signals. The local oscillator is configured to receive the one or more chirp control signals and generate a frame including a first sequence of chirps according to the one or more chirp control signals. The modulator is configured to modulate the first sequence of chirps to generate a second sequence of chirps so the frame includes the first sequence of chirps and the second sequence of chirps offset by a first frequency value.
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公开(公告)号：US11231484B2
公开(公告)日：2022-01-25
申请号：US16816588
申请日：2020-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Karthik Subburaj , Brian Paul Ginsburg , Daniel Colum Breen , Sandeep Rao , Karthik Ramasubramanian
IPC: G01S7/40 , G01S7/03 , G01S7/35 , G01S13/931 , G01S13/02
Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.
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公开(公告)号：US11194017B2
公开(公告)日：2021-12-07
申请号：US16984262
申请日：2020-08-04
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Indu Prathapan , Karthik Ramasubramanian , Brian P. Ginsburg
Abstract: A FMCW radar system with a built-in self-test (BIST) system for monitoring includes a receiver, a transmitter, and a frequency synthesizer. A FMCW chirp timing engine controls timing of operations at least one radar component. The BIST system includes at least one switchable coupling for coupling a first plurality of different analog signals including from a first plurality of selected nodes in the receiver or transmitter that are all coupled to a second number of monitor analog-to-digital converters (ADCs). The second number is less than (
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Patent Agency Ranking
公开(公告)号：US11023323B2
公开(公告)日：2021-06-01
申请号：US16788004
申请日：2020-02-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian , Brian Paul Ginsburg
Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.
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公开(公告)号：US10782389B2
公开(公告)日：2020-09-22
申请号：US15676547
申请日：2017-08-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian , Brian Ginsburg , Jawaharial Tangudu , Karthik Subburaj
IPC: G01S7/03 , G01S13/34 , G01S13/931 , H01Q1/32
Abstract: A device includes a circuit board having thereon, a controlling component, a first radar chip and a second radar chip. The first radar chip includes a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array. The second radar chip includes a second radar receiver antenna array. The controlling component can control the first radar chip and the second radar chip. The first radar transmission antenna can transmit a first radar transmission signal. The second radar transmission antenna can transmit a second radar transmission signal. The second radar chip is spaced from the first radar chip so as to create a virtual receiver antenna array between the first radar receiver antenna array and the second radar receiver antenna array.
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公开(公告)号：US20180372840A1
公开(公告)日：2018-12-27
申请号：US16107000
申请日：2018-08-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian
Abstract: The disclosure provides a radar apparatus. The radar apparatus includes a transmitter that transmits a first chirp. The first chirp is scattered by one or more obstacles to generate a first plurality of scattered signals. A plurality of receivers receives the first plurality of scattered signals. Each receiver of the plurality of receivers generates a digital signal in response to a scattered signal of the first plurality of scattered signals. A processor is coupled to the plurality of receivers and receives the digital signals from the plurality of receivers. The processor performs range FFT (fast fourier transform) and angle FFT on the digital signals received from the plurality of receivers to generate a first matrix of complex samples.
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公开(公告)号：US20170363714A1
公开(公告)日：2017-12-21
申请号：US15676547
申请日：2017-08-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian , Brian Ginsburg , Jawaharial Tangudu , Karthik Subburaj
CPC classification number: G01S7/032 , G01S13/343 , G01S13/931 , H01Q1/3233
Abstract: A device includes a circuit board having thereon, a controlling component, a first radar chip and a second radar chip. The first radar chip includes a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array. The second radar chip includes a second radar receiver antenna array. The controlling component can control the first radar chip and the second radar chip. The first radar transmission antenna can transmit a first radar transmission signal. The second radar transmission antenna can transmit a second radar transmission signal. The second radar chip is spaced from the first radar chip so as to create a virtual receiver antenna array between the first radar receiver antenna array and the second radar receiver antenna array.
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公开(公告)号：US20170315211A1
公开(公告)日：2017-11-02
申请号：US15642880
申请日：2017-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Karthik Subburaj , Brian Ginsburg , Karthik Ramasubramanian
Abstract: The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.
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