公开(公告)号：JP2007036095A

公开(公告)日：2007-02-08

申请号：JP2005220396

申请日：2005-07-29

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  KAWAMOTO KENJI ,  SEKINE HIDEKATSU

IPC: H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a wiring circuit board having built-in passive elements, which circuit board contains a capacitance element having superior capacitance value precision and a resistance element adjusted exactly by trimming, and to provide a manufacturing method for the circuit board.
SOLUTION: According to the wiring board having the built-in passive elements, at least one wiring layer, vias, and passive elements are formed via an insulating layer 33. The passive elements consist of the capacitance element 40 and the resistance element 50. The capacitance element 40 is formed in such a way that a dielectric layer 21 is sandwiched between a capacitance element upper electrode 13a and a capacitance element lower electrode 12a. The resistance element 50 is formed on the insulating layer 33 on the dielectric layer 21. The capacitance element 40 is separated from the resistance element 50 across the insulating layer 33.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种具有内置无源元件的布线电路板，该电路板包含具有优异的电容值精度的电容元件和精确调整的电阻元件，并且提供一种用于 电路板。 解决方案：根据具有内置无源元件的布线板，通过绝缘层33形成至少一个布线层，通孔和无源元件。无源元件由电容元件40和电阻元件 电容元件40形成为使电介质层21夹在电容元件上部电极13a和电容元件下部电极12a之间。 电阻元件50形成在电介质层21上的绝缘层33上。电容元件40跨越绝缘层33与电阻元件50分离。版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004339260A

公开(公告)日：2004-12-02

申请号：JP2003133926

申请日：2003-05-13

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SHIROMIZU KOHEI ,  SATO JIN

IPC: B32B27/18 ,  B32B27/38 ,  C08G59/42 ,  C08K3/00 ,  C08L63/00

Abstract: PROBLEM TO BE SOLVED: To obtain a dielectric photosensitive resin composition having a high sensitivity and resolution, to prepare a dry film, and to provide a printed wiring board with a highly reliable built-in capacitor element using the same. SOLUTION: The photosensitive resin composition with a high dielectric constant contains at least (A) an epoxy resin, (B) an unsaturated group-containing polycarboxylic acid obtained by reacting a reactant of an epoxy compound and an unsaturated carboxylic acid with an (un)saturated polybasic acid anhydride and (C) a dielectric filler having a dielectric constant of ≥50. A high resolution and dielectric property are imparted to the composition through the addition of ≥30 wt.% component (C) based on the total weight of the resin solid content. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004119483A

公开(公告)日：2004-04-15

申请号：JP2002277597

申请日：2002-09-24

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： KAWAMOTO KENJI ,  TONEGAWA MASAHISA ,  SATO JIN

IPC: H01G4/38 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a board having built-in elements, wherein built-in chips occupy lesser mounting areas, wherein very fine wiring patterns are formed in capacitor elements built to decrease part accommodating layer thickness and in the circuit board, and wherein chip passive parts such as LCR (inductance, capacitance, resistance) elements are accurately mounted while they are being connected to the wiring patterns.
SOLUTION: The board having built-in elements is a printed circuit board having one or more insulating layers. The capacitor elements are built in the insulating layers, and are constituted of a plurality of electrodes and dielectric layers which are alternately stacked up. Further, when the capacitor element dielectric layers contain dielectric fillers, at least a thermoplastic resin and/or a thermosetting resin, an appropriately flexible board having built-in elements is manufactured.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2012074449A

公开(公告)日：2012-04-12

申请号：JP2010216734

申请日：2010-09-28

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： HAYASHI AKIHIRO ,  CHINO MASAAKI ,  SATO JIN

IPC: H01L23/12 ,  H01L21/60 ,  H05K3/34

CPC classification number: H01L2224/16225 ,  H01L2224/32225

Abstract: PROBLEM TO BE SOLVED: To provide a mounting substrate having improving reliability with suppressed void occurrence and having underfill filled in a short time, in the mounting substrate in which an IC chip connection terminal is electrically connected to a conductor pattern via solder laid on openings formed on a solder resist, and a gap between the solder resist and the IC chip other than the electrical connection portion is filled with the underfill.SOLUTION: A portion of a solder resist 6r coated with underfill 7 includes grooves 9a having a narrower width than the disposition pitch of the connection openings. Each groove 9a is formed between the connection openings in a manner to be stitched into a stripe shape, or to surround the opening in a grid shape, a polygonal shape, a circular shape or an elliptical shape, or to be stitched into a wave shape. The cross sectional shape of each groove 9a is U-shaped, V-shaped or rectangular-shaped.

Abstract translation: 要解决的问题：为了提供一种安装基板，其中IC芯片连接端子通过焊接布置电连接到导体图案的安装基板中，具有提高的可靠性，抑制空隙发生并且在短时间内填充底部填充物 在形成在阻焊剂上的开口上，除了电连接部分之外的阻焊剂和IC芯片之间的间隙填充有底部填充物。 解决方案：涂覆有底部填充剂7的阻焊剂6r的一部分包括具有比连接开口的布置间距窄的宽度的槽9a。 每个槽9a以缝合成条状的方式形成在连接开口之间，或者围绕开口形成为格子状，多边形，圆形或椭圆形，或者被缝合成波形 。 每个槽9a的横截面形状是U形，V形或矩形。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2012069889A

公开(公告)日：2012-04-05

申请号：JP2010215626

申请日：2010-09-27

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： HISHIKAWA TOSHIYUKI ,  SATO JIN

IPC: H05K1/02 ,  H01L23/12

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer wiring board, having improved ion migration resistance between adjacent signal lines with added contrivance on a wiring pattern.SOLUTION: The multilayer wiring board includes multilayer wiring having a plurality of wiring layers alternately laminated with interlayer insulation layers that are composed of an insulation resin disposed between the wiring layers. A wiring layer placed in the outermost layer of the wiring layers further includes a semiconductor mounting portion for mounting a semiconductor to be connected to a signal line. In the multilayer wiring board, a wiring layer on the outermost layer of the wiring layers includes a plurality of signal lines 1 (1A, 1B). The plurality of signal lines include signal lines 1A having convex-shaped convex portions 2 formed in a direction close to other adjacent signal lines 1B. The contour of each convex portion 2 is bordered with a curve. The curve is formed of a circular arc having a predefined curvature.

Abstract translation: 要解决的问题：提供一种多层布线板，其具有在相邻信号线之间改进的离子迁移电阻，并且在布线图案上增加了设计。 解决方案：多层布线板包括具有交替层叠层间绝缘层的多个布线层的多层布线，层间绝缘层由设置在布线层之间的绝缘树脂构成。 放置在布线层的最外层的布线层还包括用于安装要连接到信号线的半导体的半导体安装部分。 在多层布线基板中，布线层的最外层的布线层包括多个信号线1（1A，1B）。 多条信号线包括形成在靠近其它相邻信号线1B的方向上的凸形凸部2的信号线1A。 每个凸部2的轮廓与曲线相邻。 曲线由具有预定曲率的圆弧形成。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2010238917A

公开(公告)日：2010-10-21

申请号：JP2009085364

申请日：2009-03-31

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  CHINO MASAAKI ,  FURUYA AKIHIKO

IPC: H01L23/12

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a photosensitive resist protecting tape that is effective for the supply of a semiconductor package substrate not deteriorating a loading yield and connecting reliability, and high in electric reliability even if an aperture diameter of a solder resist is further reduced, and also to provide a method of manufacturing the semiconductor package substrate, and the semiconductor package substrate. SOLUTION: The photosensitive resist protecting tape is formed of a base material film 2a, an adhesive layer 2c, and a supporting film 2b. The protecting tape is characterized in that the base material film 2a, the adhesive layer 2c, and a light-hardening resin of the solder resist are laminated in this order, and the base material film or the adhesive layer is imparted with optical characteristics that: (1) the transmittance of the base material film and the adhesive layer for the exposure light of the solder resist is enough to permit the light of 350 to 450 nm of the exposure light to reach SR; and (2) a ratio of the main peak intensity of the light in a 350 to 380 nm region and the main peak intensity of light in a 400 to 420 nm region is in a range of 1:1 to 1:5. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种对半导体封装基板的供给有效的光敏抗蚀剂保护带，即使阻焊剂的孔径直径是不变的，也不会降低负载成品率和连接可靠性，并且电可靠性高 并且还提供制造半导体封装基板的方法和半导体封装基板。 光敏抗蚀剂保护带由基材膜2a，粘合剂层2c和支撑膜2b形成。 保护带的特征在于，基材材料膜2a，粘合剂层2c和阻焊剂的光硬化树脂依次层叠，并且赋予基材膜或粘合剂层以下光学特性： （1）基材薄膜和阻焊剂的曝光用粘合剂层的透射率足以使曝光光的350〜450nm的光达到SR; （2）350〜380nm区域的光的主峰强度与400〜420nm区域的主峰强度的比例为1:1〜1:5。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008147228A

公开(公告)日：2008-06-26

申请号：JP2006329256

申请日：2006-12-06

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SEKINE HIDEKATSU ,  KAWAMOTO KENJI ,  SATO JIN

IPC: H05K3/46 ,  H01L23/12 ,  H05K1/16 ,  H05K1/18

CPC classification number: H01L2224/18 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To realize downsizing by improving positioning accuracy between the respective layers of a wiring board and electronic parts and to reduce manufacturing time and costs by incorporating electronic parts such as semiconductor element, capacitor, resistor, inductor or the like in the wiring board at the same time. SOLUTION: Electronic parts such as semiconductor element, capacitor, resistor and inductor are built in the wiring board. When stacking the layers, they are positioned by sprocket holes or the like of a film carrier wherein the electronic parts are mounted, so as to improve the positioning accuracy between the respective layers of the wiring board and the electronic parts. Furthermore, an ILB connection technology that is technologically established is used to cope with narrower pitches of semiconductor elements, stable reliability of connection and shortest wiring to the upper layer for downsizing. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了通过提高布线板和电子部件的各个层之间的定位精度来实现小型化，并且通过结合诸如半导体元件，电容器，电阻器，电感器等的电子部件来减少制造时间和成本 在接线板上同时进行。

解决方案：电路板内装有半导体元件，电容器，电阻和电感等电子部件。 当堆叠层时，它们通过其中安装电子部件的胶片载体的链轮等定位，以提高布线板和电子部件的各个层之间的定位精度。 此外，技术上建立的ILB连接技术用于处理半导体元件的较窄的间距，稳定的连接可靠性和最小布线到上层以减小尺寸。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008124260A

公开(公告)日：2008-05-29

申请号：JP2006306706

申请日：2006-11-13

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SEKINE HIDEKATSU ,  KAWAMOTO KENJI ,  SATO JIN

IPC: H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer wiring substrate and a manufacturing method thereof wherein its electronic component is connected with its upper-layer circuit without performing any via-hole processing by a laser, and its lands can be formed even though such a tendency that the electrode pitch of its electronic component is forced to be narrowed proceeds.
SOLUTION: The multilayer wiring substrate according to an embodiment of this invention has: a wiring substrate 100 whereon an insulating layer 6 and wirings 8 are laminated; an electronic component 3 having a plurality of electrodes 1 arranged at a predetermined pitch and having a plurality of bumps 2 formed on the respective electrodes 1; and a plurality of lands 7 for connecting the plurality of bumps 2 with the wirings 8 of its upper-layer circuit. Hereupon, the plurality of bumps 2 has respectively flat planes on their upper portions, and the respective flat planes are connected directly with the plurality of lands 7.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种多层布线基板及其制造方法，其电子部件与上层电路连接而不进行激光的通孔处理，即使在其上也可形成 电子部件的电极间距被迫变窄的倾向。 解决方案：根据本发明实施例的多层布线基板具有：层叠有绝缘层6和布线8的布线基板100; 电子部件3，具有以规定的间距配置的多个电极1，具有形成在各电极1上的多个凸块2; 以及用于将多个凸块2与其上层电路的布线8连接的多个焊盘7。 因此，多个凸块2在其上部分别具有平面，并且各个平面直接与多个焊盘7连接。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008091377A

公开(公告)日：2008-04-17

申请号：JP2006267205

申请日：2006-09-29

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  KAWAMOTO KENJI ,  FURUYA AKIHIKO ,  SEKINE HIDEKATSU

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To increase density of a wiring pattern of a printed wiring board incorporating a semiconductor chip. SOLUTION: An element incorporated center layer substrate and a chip device accommodated in a cavity formed on the center layer substrate are provided on a first insulation layer. An electrode pattern is provided on a surface of the center layer substrate. The element incorporated center layer substrate has an element formed by electrically connecting with the electrode pattern. The first insulation layer has a conductive part made of a via hole filled with a conductive resin composition at a position connected with the chip device. A second insulation layer is provided on the element incorporated center layer substrate and the chip device. A via hole with a smaller area than that of the electrode pattern is provided on the electrode pattern. The via hole is electrically connected with the wiring pattern on the surface of the second insulation layer. The printed wiring board is thus manufactured. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：增加包含半导体芯片的印刷线路板的布线图案的密度。 解决方案：在第一绝缘层上设置包含中心层基板的元件和容纳在形成在中心层基板上的空腔中的芯片装置。 电极图案设置在中心层基板的表面上。 元件结合的中心层基板具有通过与电极图案电连接形成的元件。 第一绝缘层具有由与芯片装置连接的位置填充有导电性树脂组合物的通路孔构成的导电部。 在元件结合的中心层基板和芯片装置上设置第二绝缘层。 在电极图案上设置有比电极图案小的面积的通孔。 通孔与第二绝缘层的表面上的布线图形电连接。 由此制造印刷电路板。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2010225990A

公开(公告)日：2010-10-07

申请号：JP2009073566

申请日：2009-03-25

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： AZUMA NAO ,  SATO JIN

IPC: H05K3/46 ,  H05K3/24

Abstract: PROBLEM TO BE SOLVED: To provide a printed circuit board with a built-in printing element which is superior in forming accuracy, does not cause disconnection which may be caused by electrochemical reaction during the process for increasing surface roughness before lamination, and have small property fluctuation in high temperature, high moisture test. SOLUTION: In the printed circuit board having one or more printed elements arranged on at least one layer of the wiring layer, a wiring to be connected to the printing element is formed of copper, an electrode of the printing element is made such that part of the copper wiring is covered with different metal plating, and a printing element is arranged between the electrode covered with the metal plating and the electrode. The upper boundary and side of the metal plating and copper wiring are covered with a protective layer. Furthermore, the protective layer has a structure independent of the printing element. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了提供具有优异的成形精度的内置打印元件的印刷电路板，不会在层压之前增加表面粗糙度的工艺期间由电化学反应引起的断开，以及 在高温，高湿度试验中具有小的物性波动。 解决方案：在具有布置在至少一层布线层上的一个或多个印刷元件的印刷电路板中，要连接到印刷元件的布线由铜形成，印刷元件的电极被制成 铜线的一部分被不同的金属电镀覆盖，并且印刷元件布置在被金属电镀覆盖的电极和电极之间。 金属镀层和铜线的上边界和侧面被保护层覆盖。 此外，保护层具有独立于印刷元件的结构。 版权所有（C）2011，JPO＆INPIT