公开(公告)号：JP2007324297A

公开(公告)日：2007-12-13

申请号：JP2006151511

申请日：2006-05-31

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SEKINE HIDEKATSU ,  KAWAMOTO KENJI ,  SATO JIN

IPC: H05K1/16

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board that incorporates a capacitor by which a change in shape of a dielectric can be reduced and the accuracy of the capacitor capacity in a substrate can be improved in the method of manufacturing the printed wiring board.
SOLUTION: A wiring layer 21a and a wiring layer 21b are formed on one surface of an insulating substrate 11, and a conductor layer 22 is formed on the other surface thereof, so as to manufacture a wiring board midway of a process. Next, a dielectric layer 31 and a conductor layer 25 are formed on the conductor layer 22, and the conductor layer 25 is patterned to form a capacitor upper electrode 25a. Furthermore, the dielectric layer 31 is patterned to form a dielectric 31a. The dielectric layer, protruding from the capacitor upper electrode 25a, is removed by blasting method, so as to form a dielectric 31b having corrected shape. The conductor layer 24 is patterned to form a capacitor lower electrode 24a, and a wiring board 100 incorporating a capacitor is obtained.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造布线板的方法，该布线板包括电容器，通过该电容器可以降低电介质的形状变化，并且可以提高基板中的电容器容量的精度， 制造印刷电路板。 解决方案：在绝缘基板11的一个表面上形成布线层21a和布线层21b，并且在其另一个表面上形成导体层22，以便在工艺中途制造布线板。 接着，在导体层22上形成介质层31和导体层25，对导体层25进行图案化，形成电容器上部电极25a。 此外，电介质层31被图案化以形成电介质31a。 从电容器上部电极25a突出的电介质层通过喷砂法除去，形成具有校正形状的电介质31b。 导体层24被图案化以形成电容器下电极24a，并且获得并入电容器的布线板100。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007201326A

公开(公告)日：2007-08-09

申请号：JP2006020350

申请日：2006-01-30

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SEKINE HIDEKATSU ,  KAWAMOTO KENJI ,  SATO JIN

IPC: H05K3/46 ,  H01L23/12 ,  H05K3/40

Abstract: PROBLEM TO BE SOLVED: To provide a wiring board with built-in elements and a manufacturing method therefor, wherein the manufacturing time of built in capacitors is reduced in cost-affective manner. SOLUTION: Each of capacitors 1 includes a first electrode 4 of a conductive paste hardened material, a second electrode 2 of a metal foil, and a dielectric layer 8 sandwiched between them; and the first electrode is made conductive to an external wiring 5 through a via 15 penetrated through the dielectric layer. The manufacturing method includes a step (1) of forming a sheet member, comprising the metal foil layer and the dielectric layer; a step (2) of printing and laying out a conductive paste to the dielectric layer and curing the paste to form the first electrode; a step (3) of laminating a side of the function electrode to another wiring board via a prepreg; a step (4) of forming the via hole penetrated through the metal foil layer and reaching the first electrode; a step (5) of filling a conductive material to the via hole to form the via; a step (6) of forming an etching resist to a side of the metallic foil layer; and a step (7) of etching the metal foil layer to form the second electrode. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供具有内置元件的布线板及其制造方法，其中内置电容器的制造时间以成本效益的方式降低。 解决方案：每个电容器1包括导电浆料硬化材料的第一电极4，金属箔的第二电极2和夹在它们之间的电介质层8; 并且第一电极通过穿过电介质层的通孔15而导电到外部配线5。 该制造方法包括形成片状部件的步骤（1），该片材部件包括金属箔层和电介质层; 将导电浆料印刷并布置到电介质层并固化糊料以形成第一电极的步骤（2）; 将功能电极的一侧经由预浸料层压到另一配线基板上的工序（3） 形成穿过所述金属箔层并到达所述第一电极的所述通孔的步骤（4）; 将导电材料填充到通孔以形成通孔的步骤（5）; 在所述金属箔层侧形成抗蚀剂的工序（6） 以及蚀刻金属箔层以形成第二电极的步骤（7）。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2008016552A

公开(公告)日：2008-01-24

申请号：JP2006184572

申请日：2006-07-04

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： KUMAI KOICHI ,  AKIYAMA NAOYUKI ,  SATO JIN ,  KAWAMOTO KENJI

IPC: H05K3/46 ,  H05K3/32

Abstract: PROBLEM TO BE SOLVED: To provide a component-mounting substrate and a manufacturing method therefor having low manufacturing cost and high product quality.
SOLUTION: In the manufacturing method of the component-mounting substrate, a multilayer printed wiring board 20 is previously prepared, wherein insulating layers and wiring layers 21 having wirings and vacant portions alternately are so laminated as to position the wiring layer 21 in the outermost layer in thickness direction. Also, a conductive-resin pattern 11 is formed, by applying a plastic conductive resin to a surface of a support sheet 10 which is present in its thickness direction. Furthermore, an element 12 is formed in the conductive resin which constitutes the conductive-resin pattern 11 in the surface of the support sheet 10. Moreover, the element 12 is so inserted into the vacant portion and the surface with the conductive-resin pattern 11 formed thereon is superimposed on the wiring layer 21 of the multilayer printed wiring board 20, to bond pressingly the support sheet 10 to the multilayer printed wiring board 20. Furthermore, the support sheet 10 is peeled from the multilayer printed wiring board 20 to transcribe the conductive-resin pattern 11 and the element 12 on the wiring layer 21. Consequently, the component mounting substrate is obtained.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有低制造成本和高产品质量的部件安装基板及其制造方法。 解决方案：在组件安装基板的制造方法中，预先制备多层印刷布线板20，其中交替布置有布线层和空位部分的绝缘层和布线层21，以将布线层21定位在 厚度方向的最外层。 此外，通过将塑料导电树脂施加到沿其厚度方向存在的支撑片材10的表面上，形成导电树脂图案11。 此外，在支撑片10的表面中构成导电树脂图案11的导电树脂中形成元件12.此外，元件12被插入到空的部分中，并且表面与导电树脂图案11 叠层在多层印刷电路板20的布线层21上，将支撑片10按压到多层印刷电路板20上。此外，支撑片10从多层印刷线路板20剥离， 导电树脂图案11和布线层21上的元件12。因此，获得部件安装基板。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007036095A

公开(公告)日：2007-02-08

申请号：JP2005220396

申请日：2005-07-29

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  KAWAMOTO KENJI ,  SEKINE HIDEKATSU

IPC: H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a wiring circuit board having built-in passive elements, which circuit board contains a capacitance element having superior capacitance value precision and a resistance element adjusted exactly by trimming, and to provide a manufacturing method for the circuit board.
SOLUTION: According to the wiring board having the built-in passive elements, at least one wiring layer, vias, and passive elements are formed via an insulating layer 33. The passive elements consist of the capacitance element 40 and the resistance element 50. The capacitance element 40 is formed in such a way that a dielectric layer 21 is sandwiched between a capacitance element upper electrode 13a and a capacitance element lower electrode 12a. The resistance element 50 is formed on the insulating layer 33 on the dielectric layer 21. The capacitance element 40 is separated from the resistance element 50 across the insulating layer 33.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种具有内置无源元件的布线电路板，该电路板包含具有优异的电容值精度的电容元件和精确调整的电阻元件，并且提供一种用于 电路板。 解决方案：根据具有内置无源元件的布线板，通过绝缘层33形成至少一个布线层，通孔和无源元件。无源元件由电容元件40和电阻元件 电容元件40形成为使电介质层21夹在电容元件上部电极13a和电容元件下部电极12a之间。 电阻元件50形成在电介质层21上的绝缘层33上。电容元件40跨越绝缘层33与电阻元件50分离。版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004339260A

公开(公告)日：2004-12-02

申请号：JP2003133926

申请日：2003-05-13

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SHIROMIZU KOHEI ,  SATO JIN

IPC: B32B27/18 ,  B32B27/38 ,  C08G59/42 ,  C08K3/00 ,  C08L63/00

Abstract: PROBLEM TO BE SOLVED: To obtain a dielectric photosensitive resin composition having a high sensitivity and resolution, to prepare a dry film, and to provide a printed wiring board with a highly reliable built-in capacitor element using the same. SOLUTION: The photosensitive resin composition with a high dielectric constant contains at least (A) an epoxy resin, (B) an unsaturated group-containing polycarboxylic acid obtained by reacting a reactant of an epoxy compound and an unsaturated carboxylic acid with an (un)saturated polybasic acid anhydride and (C) a dielectric filler having a dielectric constant of ≥50. A high resolution and dielectric property are imparted to the composition through the addition of ≥30 wt.% component (C) based on the total weight of the resin solid content. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004119483A

公开(公告)日：2004-04-15

申请号：JP2002277597

申请日：2002-09-24

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： KAWAMOTO KENJI ,  TONEGAWA MASAHISA ,  SATO JIN

IPC: H01G4/38 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a board having built-in elements, wherein built-in chips occupy lesser mounting areas, wherein very fine wiring patterns are formed in capacitor elements built to decrease part accommodating layer thickness and in the circuit board, and wherein chip passive parts such as LCR (inductance, capacitance, resistance) elements are accurately mounted while they are being connected to the wiring patterns.
SOLUTION: The board having built-in elements is a printed circuit board having one or more insulating layers. The capacitor elements are built in the insulating layers, and are constituted of a plurality of electrodes and dielectric layers which are alternately stacked up. Further, when the capacitor element dielectric layers contain dielectric fillers, at least a thermoplastic resin and/or a thermosetting resin, an appropriately flexible board having built-in elements is manufactured.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2012074449A

公开(公告)日：2012-04-12

申请号：JP2010216734

申请日：2010-09-28

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： HAYASHI AKIHIRO ,  CHINO MASAAKI ,  SATO JIN

IPC: H01L23/12 ,  H01L21/60 ,  H05K3/34

CPC classification number: H01L2224/16225 ,  H01L2224/32225

Abstract: PROBLEM TO BE SOLVED: To provide a mounting substrate having improving reliability with suppressed void occurrence and having underfill filled in a short time, in the mounting substrate in which an IC chip connection terminal is electrically connected to a conductor pattern via solder laid on openings formed on a solder resist, and a gap between the solder resist and the IC chip other than the electrical connection portion is filled with the underfill.SOLUTION: A portion of a solder resist 6r coated with underfill 7 includes grooves 9a having a narrower width than the disposition pitch of the connection openings. Each groove 9a is formed between the connection openings in a manner to be stitched into a stripe shape, or to surround the opening in a grid shape, a polygonal shape, a circular shape or an elliptical shape, or to be stitched into a wave shape. The cross sectional shape of each groove 9a is U-shaped, V-shaped or rectangular-shaped.

Abstract translation: 要解决的问题：为了提供一种安装基板，其中IC芯片连接端子通过焊接布置电连接到导体图案的安装基板中，具有提高的可靠性，抑制空隙发生并且在短时间内填充底部填充物 在形成在阻焊剂上的开口上，除了电连接部分之外的阻焊剂和IC芯片之间的间隙填充有底部填充物。 解决方案：涂覆有底部填充剂7的阻焊剂6r的一部分包括具有比连接开口的布置间距窄的宽度的槽9a。 每个槽9a以缝合成条状的方式形成在连接开口之间，或者围绕开口形成为格子状，多边形，圆形或椭圆形，或者被缝合成波形 。 每个槽9a的横截面形状是U形，V形或矩形。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2012069889A

公开(公告)日：2012-04-05

申请号：JP2010215626

申请日：2010-09-27

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： HISHIKAWA TOSHIYUKI ,  SATO JIN

IPC: H05K1/02 ,  H01L23/12

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer wiring board, having improved ion migration resistance between adjacent signal lines with added contrivance on a wiring pattern.SOLUTION: The multilayer wiring board includes multilayer wiring having a plurality of wiring layers alternately laminated with interlayer insulation layers that are composed of an insulation resin disposed between the wiring layers. A wiring layer placed in the outermost layer of the wiring layers further includes a semiconductor mounting portion for mounting a semiconductor to be connected to a signal line. In the multilayer wiring board, a wiring layer on the outermost layer of the wiring layers includes a plurality of signal lines 1 (1A, 1B). The plurality of signal lines include signal lines 1A having convex-shaped convex portions 2 formed in a direction close to other adjacent signal lines 1B. The contour of each convex portion 2 is bordered with a curve. The curve is formed of a circular arc having a predefined curvature.

Abstract translation: 要解决的问题：提供一种多层布线板，其具有在相邻信号线之间改进的离子迁移电阻，并且在布线图案上增加了设计。 解决方案：多层布线板包括具有交替层叠层间绝缘层的多个布线层的多层布线，层间绝缘层由设置在布线层之间的绝缘树脂构成。 放置在布线层的最外层的布线层还包括用于安装要连接到信号线的半导体的半导体安装部分。 在多层布线基板中，布线层的最外层的布线层包括多个信号线1（1A，1B）。 多条信号线包括形成在靠近其它相邻信号线1B的方向上的凸形凸部2的信号线1A。 每个凸部2的轮廓与曲线相邻。 曲线由具有预定曲率的圆弧形成。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2010238917A

公开(公告)日：2010-10-21

申请号：JP2009085364

申请日：2009-03-31

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  CHINO MASAAKI ,  FURUYA AKIHIKO

IPC: H01L23/12

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a photosensitive resist protecting tape that is effective for the supply of a semiconductor package substrate not deteriorating a loading yield and connecting reliability, and high in electric reliability even if an aperture diameter of a solder resist is further reduced, and also to provide a method of manufacturing the semiconductor package substrate, and the semiconductor package substrate. SOLUTION: The photosensitive resist protecting tape is formed of a base material film 2a, an adhesive layer 2c, and a supporting film 2b. The protecting tape is characterized in that the base material film 2a, the adhesive layer 2c, and a light-hardening resin of the solder resist are laminated in this order, and the base material film or the adhesive layer is imparted with optical characteristics that: (1) the transmittance of the base material film and the adhesive layer for the exposure light of the solder resist is enough to permit the light of 350 to 450 nm of the exposure light to reach SR; and (2) a ratio of the main peak intensity of the light in a 350 to 380 nm region and the main peak intensity of light in a 400 to 420 nm region is in a range of 1:1 to 1:5. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种对半导体封装基板的供给有效的光敏抗蚀剂保护带，即使阻焊剂的孔径直径是不变的，也不会降低负载成品率和连接可靠性，并且电可靠性高 并且还提供制造半导体封装基板的方法和半导体封装基板。 光敏抗蚀剂保护带由基材膜2a，粘合剂层2c和支撑膜2b形成。 保护带的特征在于，基材材料膜2a，粘合剂层2c和阻焊剂的光硬化树脂依次层叠，并且赋予基材膜或粘合剂层以下光学特性： （1）基材薄膜和阻焊剂的曝光用粘合剂层的透射率足以使曝光光的350〜450nm的光达到SR; （2）350〜380nm区域的光的主峰强度与400〜420nm区域的主峰强度的比例为1:1〜1:5。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008147228A

公开(公告)日：2008-06-26

申请号：JP2006329256

申请日：2006-12-06

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SEKINE HIDEKATSU ,  KAWAMOTO KENJI ,  SATO JIN

IPC: H05K3/46 ,  H01L23/12 ,  H05K1/16 ,  H05K1/18

CPC classification number: H01L2224/18 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To realize downsizing by improving positioning accuracy between the respective layers of a wiring board and electronic parts and to reduce manufacturing time and costs by incorporating electronic parts such as semiconductor element, capacitor, resistor, inductor or the like in the wiring board at the same time. SOLUTION: Electronic parts such as semiconductor element, capacitor, resistor and inductor are built in the wiring board. When stacking the layers, they are positioned by sprocket holes or the like of a film carrier wherein the electronic parts are mounted, so as to improve the positioning accuracy between the respective layers of the wiring board and the electronic parts. Furthermore, an ILB connection technology that is technologically established is used to cope with narrower pitches of semiconductor elements, stable reliability of connection and shortest wiring to the upper layer for downsizing. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了通过提高布线板和电子部件的各个层之间的定位精度来实现小型化，并且通过结合诸如半导体元件，电容器，电阻器，电感器等的电子部件来减少制造时间和成本 在接线板上同时进行。

解决方案：电路板内装有半导体元件，电容器，电阻和电感等电子部件。 当堆叠层时，它们通过其中安装电子部件的胶片载体的链轮等定位，以提高布线板和电子部件的各个层之间的定位精度。 此外，技术上建立的ILB连接技术用于处理半导体元件的较窄的间距，稳定的连接可靠性和最小布线到上层以减小尺寸。 版权所有（C）2008，JPO＆INPIT