公开(公告)号：US09953988B2

公开(公告)日：2018-04-24

申请号：US15635165

申请日：2017-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US20170373073A1

公开(公告)日：2017-12-28

申请号：US15686169

申请日：2017-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US20170263597A1

公开(公告)日：2017-09-14

申请号：US15604685

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768 ,  H01L27/11 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

公开(公告)号：US09761302B1

公开(公告)日：2017-09-12

申请号：US15092613

申请日：2016-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Lu ,  Chang-Hung Chen ,  Chun-Hsien Huang ,  Han-Tsun Wang ,  Jheng-Tai Yan ,  Yu-Tse Kuo

IPC: G11C11/34 ,  G11C11/417 ,  G11C11/412 ,  H01L27/105

CPC classification number: G11C11/417 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1104

Abstract: A SRAM cell includes a first pass-gate device and a second-pass gate device comprising a first conductivity type, a first pull-down device and a second pull-down device comprising the first conductivity type, and a first pull-up device and a second pull-up device comprising a second conductivity type complementary to the first conductivity type. The first pass-gate device and the second pass-gate device respectively include first lightly-doped drains (hereinafter abbreviated as LDDs. The first pull-down device and the second pull-down device respectively include second LDDs. And a dosage of the first LDDs is different from a dosage of the second LDDs.

公开(公告)号：US09728541B1

公开(公告)日：2017-08-08

申请号：US15185043

申请日：2016-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US09401366B1

公开(公告)日：2016-07-26

申请号：US14792636

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Lu ,  Chang-Hung Chen ,  Yu-Tse Kuo ,  Chun-Hsien Huang

IPC: G11C11/00 ,  H01L27/088 ,  H01L27/11 ,  H01L27/02 ,  H01L29/06 ,  G11C11/412 ,  H01L21/84 ,  H01L27/105 ,  H01L29/423

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/845 ,  H01L27/1052 ,  H01L29/42392

Abstract: The present invention provides a layout pattern of an 8-transistor static random access memory (8T-SRAM), at least including a first diffusion region, a second diffusion region and a third diffusion region disposed on a substrate, a critical dimension region being disposed between the first diffusion region and the third diffusion region. The critical dimension region directly contacts the first diffusion region and the third diffusion region, a first extra diffusion region, a second extra diffusion region and a third extra diffusion region disposed surrounding and directly contacting the first diffusion region, the second diffusion region and the third diffusion region respectively. The first, the second and the third extra diffusion region are not disposed within the critical dimension region.

Abstract translation: 本发明提供了至少包括第一扩散区域，第二扩散区域和设置在衬底上的第三扩散区域的8-晶体管静态随机存取存储器（8T-SRAM）的布局图案，设置临界尺寸区域 在第一扩散区域和第三扩散区域之间。 临界尺寸区域直接接触第一扩散区域和第三扩散区域，第一额外扩散区域，第二额外扩散区域和设置在第一扩散区域，第二扩散区域和第三扩散区域周围并直接接触的第三额外扩散区域 扩散区。 第一，第二和第三附加扩散区域不设置在临界尺寸区域内。

公开(公告)号：US11475952B2

公开(公告)日：2022-10-18

申请号：US17179418

申请日：2021-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng ,  Chun-Chieh Chang

IPC: G11C15/04

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

公开(公告)号：US10892013B2

公开(公告)日：2021-01-12

申请号：US16439680

申请日：2019-06-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng

IPC: G11C15/00 ,  G11C29/00 ,  G11C15/04 ,  H01L27/11 ,  H01L27/02 ,  G06F7/74

Abstract: A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.

公开(公告)号：US10410684B2

公开(公告)日：2019-09-10

申请号：US15900811

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ting-Hao Chang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shih-Hao Liang ,  Chun-Hsien Huang ,  Shu-Ru Wang ,  Hsin-Chih Yu

IPC: G11C5/02 ,  H01L27/108 ,  H01L27/105 ,  G11C11/409 ,  G11C11/419 ,  H01L27/11 ,  H01L29/786

Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.

公开(公告)号：US20180315763A1

公开(公告)日：2018-11-01

申请号：US16028442

申请日：2018-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1108 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/6681 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.