公开(公告)号：US10468493B2

公开(公告)日：2019-11-05

申请号：US16212626

申请日：2018-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ting Chiang ,  Chi-Ju Lee ,  Chih-Wei Lin ,  Bo-Yu Su ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/51

Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.

公开(公告)号：US10388749B2

公开(公告)日：2019-08-20

申请号：US16043120

申请日：2018-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang ,  Chun-Ting Chiang ,  Chih-Wei Lin ,  Bo-Yu Su ,  Chi-Ju Lee

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/06 ,  H01L29/49 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.

公开(公告)号：US20180358448A1

公开(公告)日：2018-12-13

申请号：US15641312

申请日：2017-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ting Chiang ,  Chi-Ju Lee ,  Chih-Wei Lin ,  Bo-Yu Su ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/4975 ,  H01L21/02074 ,  H01L21/28088

Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.