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公开(公告)号：US20190006484A1
公开(公告)日：2019-01-03
申请号：US16043120
申请日：2018-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , I-Fan Chang , Chun-Ting Chiang , Chih-Wei Lin , Bo-Yu Su , Chi-Ju Lee
IPC: H01L29/51 , H01L29/49 , H01L21/3213 , H01L29/06 , H01L29/423 , H01L21/28 , H01L29/08 , H01L29/66 , H01L29/78
CPC classification number: H01L29/515 , H01L21/28088 , H01L21/28247 , H01L21/32139 , H01L21/7682 , H01L21/76897 , H01L29/0649 , H01L29/0847 , H01L29/42368 , H01L29/42376 , H01L29/4966 , H01L29/4991 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66568 , H01L29/66795 , H01L29/7851
Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.
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公开(公告)号：US20190043725A1
公开(公告)日：2019-02-07
申请号：US15688852
申请日：2017-08-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： I-Fan Chang , Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , Jie-Ning Yang , Chi-Ju Lee , Chun-Ting Chiang , Bo-Yu Su , Chih-Wei Lin , Dien-Yang Lu
IPC: H01L21/28 , H01L29/66 , H01L29/423
CPC classification number: H01L21/28167 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6656
Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.
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公开(公告)号：US20160126331A1
公开(公告)日：2016-05-05
申请号：US14554068
申请日：2014-11-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chi-Ju Lee , Yao-Chang Wang , Nien-Ting Ho , Chi-Mao Hsu , Kuan-Cheng Su , Main-Gwo Chen , Hsiao-Kwang Yang , Fang-Hong Yao , Sheng-Huei Dai , Tzung-Lin Li
IPC: H01L29/423 , H01L21/02 , H01L21/28 , H01L29/49 , H01L29/51
CPC classification number: H01L29/42376 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/02244 , H01L21/02255 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/78
Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.
Abstract translation: 本发明提供了形成在电介质层的沟槽中的金属栅极结构。 金属栅极结构包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括底部和侧部，其中底部的厚度和侧部的厚度之间的比率在2-5之间。沟槽填充有金属 层。 本发明还提供一种形成金属栅极结构的方法。
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公开(公告)号：US10468493B2
公开(公告)日：2019-11-05
申请号：US16212626
申请日：2018-12-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Ting Chiang , Chi-Ju Lee , Chih-Wei Lin , Bo-Yu Su , Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , I-Fan Chang
Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
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公开(公告)号：US10388749B2
公开(公告)日：2019-08-20
申请号：US16043120
申请日：2018-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , I-Fan Chang , Chun-Ting Chiang , Chih-Wei Lin , Bo-Yu Su , Chi-Ju Lee
IPC: H01L29/51 , H01L29/423 , H01L21/3213 , H01L21/28 , H01L29/06 , H01L29/49 , H01L21/768 , H01L29/08 , H01L29/66 , H01L29/78
Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.
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Patent Agency Ranking
公开(公告)号：US20180358448A1
公开(公告)日：2018-12-13
申请号：US15641312
申请日：2017-07-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Ting Chiang , Chi-Ju Lee , Chih-Wei Lin , Bo-Yu Su , Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , I-Fan Chang
CPC classification number: H01L29/4975 , H01L21/02074 , H01L21/28088
Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
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公开(公告)号：US10366896B2
公开(公告)日：2019-07-30
申请号：US15688852
申请日：2017-08-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： I-Fan Chang , Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , Jie-Ning Yang , Chi-Ju Lee , Chun-Ting Chiang , Bo-Yu Su , Chih-Wei Lin , Dien-Yang Lu
IPC: H01L21/28 , H01L29/423 , H01L29/66
Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.
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公开(公告)号：US10186594B2
公开(公告)日：2019-01-22
申请号：US15641312
申请日：2017-07-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Ting Chiang , Chi-Ju Lee , Chih-Wei Lin , Bo-Yu Su , Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , I-Fan Chang
Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
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公开(公告)号：US10062764B1
公开(公告)日：2018-08-28
申请号：US15665397
申请日：2017-07-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , I-Fan Chang , Chun-Ting Chiang , Chih-Wei Lin , Bo-Yu Su , Chi-Ju Lee
IPC: H01L29/51 , H01L29/49 , H01L29/423 , H01L21/3213 , H01L21/28 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/78
Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.
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公开(公告)号：US09331161B1
公开(公告)日：2016-05-03
申请号：US14554068
申请日：2014-11-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chi-Ju Lee , Yao-Chang Wang , Nien-Ting Ho , Chi-Mao Hsu , Kuan-Cheng Su , Main-Gwo Chen , Hsiao-Kwang Yang , Fang-Hong Yao , Sheng-Huei Dai , Tzung-Lin Li
IPC: H01L21/02 , H01L29/423 , H01L29/49 , H01L29/51 , H01L21/28
CPC classification number: H01L29/42376 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/02244 , H01L21/02255 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/78
Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.
Abstract translation: 本发明提供了形成在电介质层的沟槽中的金属栅极结构。 金属栅极结构包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括底部和侧部，其中底部的厚度和侧部的厚度之间的比率在2-5之间。沟槽填充有金属 层。 本发明还提供一种形成金属栅极结构的方法。
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