公开(公告)号：US20190304909A1

公开(公告)日：2019-10-03

申请号：US16446590

申请日：2019-06-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC: H01L23/528 ,  H01L29/06 ,  H01L21/762 ,  H01L27/108 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US10396073B2

公开(公告)日：2019-08-27

申请号：US15610642

申请日：2017-06-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Shih-Fang Tzou

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/108 ,  H01L21/8234

Abstract: A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure.

公开(公告)号：US10312080B2

公开(公告)日：2019-06-04

申请号：US15859750

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Ching-Hsiang Chang ,  Jui-Min Lee ,  Chia-Lung Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L21/02

Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.

公开(公告)号：US10217750B1

公开(公告)日：2019-02-26

申请号：US15712133

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US10217749B2

公开(公告)日：2019-02-26

申请号：US15894947

申请日：2018-02-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ching Chen ,  Shih-Fang Tzou ,  Kuei-Hsuan Yu ,  Hui-Ling Chuang

IPC: H01L27/108 ,  H01L21/311

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate having a memory cell region and a peripheral region defined thereon is provided. Bit line structures are formed on the memory cell region. At least one gate structure is formed on the peripheral region. A spacer layer is formed covering the semiconductor substrate, the gate structure, and the bit line structures. The spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region. A first etching process is performed to the spacer layer for removing a part of the spacer layer on the memory cell region. At least a part of the spacer layer remains on the memory cell region after the first etching process. A second etching process is performed after the first etching process for removing the spacer layer remaining on the memory cell region.

公开(公告)号：US20180366323A1

公开(公告)日：2018-12-20

申请号：US15644821

申请日：2017-07-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Cheng-Hsu Huang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Shih-Fang Tzou

IPC: H01L21/02 ,  H01L21/762 ,  H01L27/108

CPC classification number: H01L21/02282 ,  H01L21/0206 ,  H01L21/02307 ,  H01L21/02312 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/76229 ,  H01L21/76237 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H2O2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.

公开(公告)号：US20180342425A1

公开(公告)日：2018-11-29

申请号：US16038196

申请日：2018-07-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Ming-Feng Kuo ,  Li-Chiang Chen

IPC: H01L21/8234 ,  H01L27/108

Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.

公开(公告)号：US20180190659A1

公开(公告)日：2018-07-05

申请号：US15856024

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chien-Ting Ho ,  Shih-Fang Tzou ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/10855 ,  H01L21/02071 ,  H01L21/28247 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894

Abstract: A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.

公开(公告)号：US09673100B2

公开(公告)日：2017-06-06

申请号：US14536696

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chien-Ting Lin ,  Shih-Fang Tzou ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L27/088 ,  H01L29/49 ,  H01L21/768

CPC classification number: H01L21/823437 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

公开(公告)号：US20160197005A1

公开(公告)日：2016-07-07

申请号：US15072370

申请日：2016-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Lung-En Kuo ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/762 ,  H01L21/027 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3105

CPC classification number: H01L21/76224 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.