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公开(公告)号:US09608062B1
公开(公告)日:2017-03-28
申请号:US15250924
申请日:2016-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: I-Ming Tseng , Wen-An Liang , Chen-Ming Huang
IPC: H01L27/088 , H01L29/06 , H01L29/78 , H01L29/08 , H01L29/66 , H01L21/762
CPC classification number: H01L29/0653 , H01L21/76224 , H01L29/0847 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: The present invention provides a semiconductor structure including a fin structure formed on a substrate, and an isolation structure formed in the fin structure. The isolation structure includes a trench, and a first dielectric layer disposed in the trench wherein the first dielectric layer includes a body portion in the bottom, a protruding portion in the top with a top surface, and a shoulder portion connecting the body portion and the protruding portion. The protruding portion has a smaller width than the body portion. The semiconductor structure further includes a second dielectric layer covering a top corner of the trench and sandwiched between the protruding portion, the shoulder portion of the first dielectric layer and the upper sidewall of the trench.
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公开(公告)号:US20170047244A1
公开(公告)日:2017-02-16
申请号:US15336811
申请日:2016-10-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Tong-Jyun Huang , Rai-Min Huang , I-Ming Tseng , Kuan-Hsien Li , Chen-Ming Huang
IPC: H01L21/762 , H01L21/308 , H01L29/06 , H01L21/8234 , H01L27/088 , H01L21/3065 , H01L21/02
CPC classification number: H01L21/76224 , H01L21/02271 , H01L21/3065 , H01L21/308 , H01L21/3081 , H01L21/3083 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/0653
Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
Abstract translation: 翅片结构切割过程包括以下步骤。 在基板中形成有四个翅片结构,其中包括第一翅片结构,第二翅片结构,第三翅片结构和第四翅片结构的四个翅片结构彼此顺序并联。 执行第一鳍结构切割处理以去除第二鳍结构和第三鳍结构的顶部部分,从而由第二鳍结构形成第一凸起,以及由第三鳍结构形成的第二凸起。 执行第二鳍结构切割处理以完全去除第二凸起和第四鳍结构,但是将第一凸起保持在第一鳍结构旁边。 此外,本发明提供了一种通过所述方法形成的翅片结构。
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公开(公告)号:US09524909B2
公开(公告)日:2016-12-20
申请号:US14696494
申请日:2015-04-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Tong-Jyun Huang , Rai-Min Huang , I-Ming Tseng , Kuan-Hsien Li , Chen-Ming Huang
IPC: H01L29/06 , H01L21/8234 , H01L21/308 , H01L21/02 , H01L27/088
CPC classification number: H01L21/76224 , H01L21/02271 , H01L21/3065 , H01L21/308 , H01L21/3081 , H01L21/3083 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/0653
Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
Abstract translation: 翅片结构切割过程包括以下步骤。 在基板中形成有四个翅片结构,其中包括第一翅片结构,第二翅片结构,第三翅片结构和第四翅片结构的四个翅片结构彼此顺序并联。 执行第一鳍结构切割处理以去除第二鳍结构和第三鳍结构的顶部部分,从而由第二鳍结构形成第一凸起,以及由第三鳍结构形成的第二凸起。 执行第二鳍结构切割处理以完全去除第二凸起和第四鳍结构,但是将第一凸起保持在第一鳍结构旁边。 此外,本发明提供了一种通过所述方法形成的翅片结构。
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公开(公告)号:US09443952B2
公开(公告)日:2016-09-13
申请号:US14506009
申请日:2014-10-03
Applicant: United Microelectronics Corp.
Inventor: Chun-Tsen Lu , Chih-Jung Su , Jian-Wei Chen , Shui-Yen Lu , Yi-Wen Chen , Po-Cheng Huang , Chen-Ming Huang , Shih-Fang Tzou
IPC: H01L21/3205 , H01L29/66 , H01L21/8234 , H01L21/3105 , H01L21/311 , H01L21/02 , H01L21/8238 , H01L29/49 , H01L29/51
CPC classification number: H01L29/66545 , H01L21/0206 , H01L21/02065 , H01L21/02271 , H01L21/31053 , H01L21/31055 , H01L21/311 , H01L21/31144 , H01L21/823431 , H01L21/823821 , H01L29/4966 , H01L29/517
Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.
Abstract translation: 公开了一种形成半导体器件的方法。 提供具有多个翅片的基板。 绝缘层填充两个相邻翅片之间的间隙的下部。 在一个翅片上形成至少一个第一堆叠结构,并且在一个绝缘层上形成至少一个第二堆叠结构。 形成第一电介质层以覆盖第一和第二堆叠结构。 去除第一电介质层的一部分和第一和第二堆叠结构的部分。 去除第一电介质层的另一部分,直到剩余的第一电介质层的顶部低于第一和第二堆叠结构的顶部。 形成第二电介质层以覆盖第一和第二堆叠结构。 去除第二电介质层的一部分直到第一和第二堆叠结构的顶部露出。
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公开(公告)号:US20230135742A1
公开(公告)日:2023-05-04
申请号:US18088631
申请日:2022-12-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ching-Ling Lin , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/8234 , H01L29/06 , H01L27/088 , H01L21/764 , H01L29/66 , H01L29/78
Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
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公开(公告)号:US20200258788A1
公开(公告)日:2020-08-13
申请号:US16859959
申请日:2020-04-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ching-Ling Lin , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/764 , H01L27/088 , H01L29/06
Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
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公开(公告)号:US10312146B2
公开(公告)日:2019-06-04
申请号:US15647031
申请日:2017-07-11
Applicant: United Microelectronics Corp.
Inventor: Ching-Ling Lin , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/8234 , H01L21/033 , H01L21/8238 , H01L21/84 , H01L21/324 , H01L21/02 , H01L27/088 , H01L29/417
Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.
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公开(公告)号:US09786502B2
公开(公告)日:2017-10-10
申请号:US15067157
申请日:2016-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuan-Hsien Li , Rai-Min Huang , I-Ming Tseng , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/033 , H01L21/8234
CPC classification number: H01L21/0337 , H01L21/823431 , H01L21/845 , H01L29/6681
Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.
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公开(公告)号:US20170263454A1
公开(公告)日:2017-09-14
申请号:US15067157
申请日:2016-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuan-Hsien Li , Rai-Min Huang , I-Ming Tseng , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/033 , H01L21/8234
CPC classification number: H01L21/0337 , H01L21/823431 , H01L21/845 , H01L29/6681
Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.
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公开(公告)号:US20170207129A1
公开(公告)日:2017-07-20
申请号:US15473614
申请日:2017-03-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: I-Ming Tseng , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/8234 , H01L23/535 , H01L27/088 , H01L29/06 , H01L21/768 , H01L29/66
CPC classification number: H01L21/823475 , H01L21/76805 , H01L21/76895 , H01L21/823431 , H01L21/823481 , H01L23/485 , H01L23/535 , H01L27/0886 , H01L29/0649 , H01L29/0653 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66515 , H01L29/66545 , H01L29/6681 , H01L29/7851
Abstract: The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is provided, wherein the fin structure has a trench, next, a first liner in the trench is formed, a first insulating layer is formed on the first liner, afterwards, a shallow trench isolation is formed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer, and a top surface of the shallow trench isolation is lower than a top surface of the first insulating layer, and a dummy gate structure is formed on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.
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