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    Through Silicon Via and Method of Forming the Same
    11.
    发明申请
    Through Silicon Via and Method of Forming the Same 有权
    通过硅通孔及其形成方法

    公开(公告)号：US20130299949A1

    公开(公告)日：2013-11-14

    申请号：US13947125

    申请日：2013-07-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsiung Huang ,  Chun-Mao Chiou ,  Hsin-Yu Chen ,  Yu-Han Tsai ,  Ching-Li Yang ,  Home-Been Cheng

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.

    Abstract translation: 本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。 绝缘层设置在通孔开口的表面上。 阻挡层设置在绝缘层的表面上。 缓冲层设置在阻挡层的表面上。 导电电极设置在缓冲层的表面上，通孔开口的其余部分被导电电极完全填充。 缓冲层的一部分还在第二表面的一侧覆盖导电电极的表面，并且所述部分与第二表面平齐。

    METHOD OF MANUFACTURING DIE SEAL RING
    12.
    发明申请
    METHOD OF MANUFACTURING DIE SEAL RING 有权

    公开(公告)号：US20210082839A1

    公开(公告)日：2021-03-18

    申请号：US17103584

    申请日：2020-11-24

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Che Huang ,  Shih-Hsien Chen ,  Ching-Li Yang ,  Chih-Sheng Chang

    IPC: H01L23/58 ,  H01L23/10 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L21/768

    Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

    CONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    13.
    发明申请
    CONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190081000A1

    公开(公告)日：2019-03-14

    申请号：US15730744

    申请日：2017-10-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

    IPC: H01L23/532 ,  H01L23/522

    Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

    Capacitor and method for fabricating the same
    15.
    发明授权
    Capacitor and method for fabricating the same 有权

    公开(公告)号：US09773860B1

    公开(公告)日：2017-09-26

    申请号：US15257930

    申请日：2016-09-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Tsung Lai ,  Ching-Li Yang ,  Yu-Cheng Tung ,  Shih-Che Huang ,  Chih-Sheng Chang

    IPC: H01L49/02

    CPC classification number: H01L28/60

    Abstract: A method for fabricating a capacitor is disclosed. First, a substrate is provided, a bottom electrode and a capacitor dielectric layer are formed on the substrate, a conductive layer is formed on the capacitor dielectric layer, a patterned hard mask is formed on the conductive layer, a patterned hard mask is used to remove part of the conductive layer to form a top electrode, the patterned hard mask is removed, and a protective layer is formed on a top surface and sidewalls of top electrode. Preferably, the protective layer includes metal oxides.

    Die Seal Ring and Method of Forming the Same
    16.
    发明申请
    Die Seal Ring and Method of Forming the Same 有权
    模具密封圈及其形成方法

    公开(公告)号：US20140367835A1

    公开(公告)日：2014-12-18

    申请号：US13921174

    申请日：2013-06-18

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Te Wei ,  Po-Chao Tsao ,  Ching-Li Yang ,  Chien-Yang Chen ,  Hui-Ling Chen ,  Guan-Kai Huang

    IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768

    CPC classification number: H01L23/562 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.

    Abstract translation: 提供了模具密封环。 模具密封环包括基材和从基材挤出的第一层。 第一层具有第一鳍环结构，并且第一鳍环结构的布局具有戳状形状。 此外，提供了一种用于形成模具密封环的方法。 提供具有有源区的衬底。 在衬底上形成图案化的牺牲层。 在图案化牺牲层的侧壁上形成间隔物。 图案化的牺牲层被去除。 通过使用间隔物作为掩模对衬底进行构图，从而同时形成Fin-FET的鳍结构和模密封环的第一层。

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    17.
    发明公开
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230326882A1

    公开(公告)日：2023-10-12

    申请号：US17735099

    申请日：2022-05-02

    Applicant: United Microelectronics Corp.

    Inventor： Hui-Lung Chou ,  Ching-Li Yang ,  Chih-Sheng Chang ,  Chien-Ting Lin

    IPC: H01L23/00 ,  H01L23/58

    CPC classification number: H01L23/564 ,  H01L23/562 ,  H01L23/585

    Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.

    Through silicon via structure
    18.
    发明申请
    Through silicon via structure 有权
    通过硅通孔结构

    公开(公告)号：US20150041961A1

    公开(公告)日：2015-02-12

    申请号：US14521456

    申请日：2014-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Yu Chen ,  Home-Been Cheng ,  Yu-Han Tsai ,  Ching-Li Yang

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.

    Abstract translation: 公开了一种硅通孔结构。 贯通硅通孔包括：基板; 设置在所述基板上并具有多个第一开口的第一电介质层，所述多个第一开口的底部位于比所述基板的原始表面低的位置; 设置在所述第一电介质层和所述基板上的通孔，所述通孔与所述多个第一开口全部不重叠， 第二电介质层，其在填充所述多个第一开口的同时，设置在所述多个第一开口内和所述通孔的侧壁上; 以及设置在所述通孔内的导电材料层，所述导电材料层在所述通孔的侧壁上具有所述第二电介质层，从而形成通硅通孔。

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