公开(公告)号：US20200251434A1

公开(公告)日：2020-08-06

申请号：US16264684

申请日：2019-02-01

Applicant: Winbond Electronics Corp.

Inventor： Yen-Jui Chu ,  Jin-Neng Wu ,  Hsin-Hung Chou ,  Chun-Hung Lin

IPC: H01L23/00

Abstract: Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

公开(公告)号：US10515853B1

公开(公告)日：2019-12-24

申请号：US16215584

申请日：2018-12-10

Applicant: Winbond Electronics Corp.

Inventor： Ching-Wei Chen ,  Cheng-Hong Wei ,  Shuo-Che Chang ,  Hung-Sheng Chen ,  Hsin-Hung Chou

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/66 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/304 ,  H01L21/784

Abstract: A method of wafer dicing is provided. The method of wafer dicing includes: providing a wafer, wherein the wafer includes a substrate, dies formed in and over the substrate and a scribe line structure located in a scribe line region between adjacent dies; removing a portion of the scribe line structure around a test device in the scribe line structure; attaching a front side of the wafer with a first tape; removing a portion of the substrate overlapping with the scribe line region from a back side of the wafer; attaching the back side of the wafer with a second tape; and removing the first tape along with the remaining portion of the scribe line structure attached thereon, leaving the dies separately attached on the second tape.

公开(公告)号：US20180151374A1

公开(公告)日：2018-05-31

申请号：US15681436

申请日：2017-08-21

Applicant: Winbond Electronics Corp.

Inventor： Yen-Jui Chu ,  Hsin-Hung Chou ,  Ming-Chih Tsai

IPC: H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  B81C1/00

Abstract: The present invention provides a patterned structure for an electronic device and a manufacturing method thereof. The patterned structure includes a patterned layer, a blocking structure, a cantilever structure, and a connection structure. The patterned layer is disposed on a substrate. The blocking structure is disposed on the substrate at one side of the patterned layer, wherein a thickness of the blocking structure is smaller than a thickness of the patterned layer. The cantilever structure is disposed on the substrate and located between the patterned layer and the blocking structure. The cantilever structure is connected with the patterned layer and the blocking structure. The connection structure is connected between the patterned layer and the substrate at one side of the patterned layer, and located on the cantilever structure and the blocking structure.