公开(公告)号：US20140112500A1

公开(公告)日：2014-04-24

申请号：US14142276

申请日：2013-12-27

Applicant: Wolfson Microelectronics plc

Inventor： John Paul Lesso

IPC: H03F3/181 ,  H03K3/013

CPC classification number: H03F3/181 ,  H03F1/304 ,  H03F3/183 ,  H03F2200/03 ,  H03K3/013

Abstract: An apparatus and method for DC offset compensation. An amplifier receives an input signal (AIN) and provides an amplified output signal (SOUT) and a feedback path provides DC offset compensation. The feedback path comprises at least one voltage controlled oscillator (VCO) and a counter. The VCO provides, over time, a first VCO output signal based on said amplified output signal and a second VCO output signal based on a reference signal (VREF). The counter generates first pulse counts based upon the first VCO output signal and second pulse counts based upon the second VCO output signal and provides a compensation signal based on a comparison of the first and second pulse counts. One voltage controlled oscillator may sequentially receive a signal based on said amplifier output signal and the reference signal from a multiplexer so as to sequentially produce the first and second VCO output signals.

Abstract translation: 一种用于直流偏移补偿的装置和方法。 放大器接收输入信号（AIN）并提供放大的输出信号（SOUT），反馈路径提供DC偏移补偿。 反馈路径包括至少一个压控振荡器（VCO）和计数器。 VCO随时间提供基于所述放大的输出信号的第一VCO输出信号和基于参考信号（VREF）的第二VCO输出信号。 计数器基于第一VCO输出信号和基于第二VCO输出信号的第二脉冲计数产生第一脉冲计数，并且基于第一和第二脉冲计数的比较来提供补偿信号。 一个压控振荡器可以基于所述放大器输出信号和来自多路复用器的参考信号顺序地接收信号，以便顺序产生第一和第二VCO输出信号。

公开(公告)号：US20130300508A1

公开(公告)日：2013-11-14

申请号：US13942303

申请日：2013-07-15

Applicant: Wolfson Microelectronics plc

Inventor： John Paul Lesso

IPC: H03F3/193

CPC classification number: H03G3/3015 ,  H03F1/0216 ,  H03F1/0227 ,  H03F1/0261 ,  H03F1/30 ,  H03F3/185 ,  H03F3/193 ,  H03F2200/03 ,  H03F2200/504 ,  H03G3/001

Abstract: An amplifier circuit, comprising: an input, for receiving an input signal to be amplified; a power amplifier, for amplifying the input signal; a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switched power supply. The dither block is controlled based on the input signal. Another aspect of the invention involves using first and second switches, each having different capacitances and resistances, and using the first or second switch depending on the input signal or volume signal. Another aspect of the invention involves controlling a bias signal provided to one or more components in the signal path based on the input signal or volume signal.

公开(公告)号：US09473098B2

公开(公告)日：2016-10-18

申请号：US14182445

申请日：2014-02-18

Applicant: Wolfson Microelectronics plc

Inventor： John Paul Lesso

IPC: H03G3/30 ,  H03F1/02 ,  H03F3/193 ,  H03F3/185 ,  H03G3/00 ,  H03F1/30

CPC classification number: H03G3/3015 ,  H03F1/0216 ,  H03F1/0227 ,  H03F1/0261 ,  H03F1/30 ,  H03F3/185 ,  H03F3/193 ,  H03F2200/03 ,  H03F2200/504 ,  H03G3/001

Abstract: An amplifier circuit comprises an input, for receiving an input signal to be amplified; a preamplifier, for amplifying the input signal based on a variable gain; a power amplifier for amplifying the signal output from the preamplifier; and a variable voltage power supply for supplying one or more supply voltages to the power amplifier. The supply voltages are adjusted based on the variable gain or the input digital signal. According to other aspects of the invention, a power supply of an amplifier circuit is clocked using a clock signal, whereby the clock signal has a frequency that varies in accordance with a volume signal or an input signal.

Abstract translation: 放大器电路包括用于接收待放大的输入信号的输入端; 前置放大器，用于基于可变增益放大输入信号; 用于放大从前置放大器输出的信号的功率放大器; 以及用于向功率放大器提供一个或多个电源电压的可变电压电源。 电源电压根据可变增益或输入数字信号进行调整。 根据本发明的其他方面，使用时钟信号对放大器电路的电源进行定时，由此时钟信号具有根据音量信号或输入信号而变化的频率。

公开(公告)号：US20150256925A1

公开(公告)日：2015-09-10

申请号：US14437685

申请日：2013-10-10

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： John Paul Lesso

IPC: H04R3/00 ,  H03M1/66

CPC classification number: H04R3/00 ,  H03M1/66 ,  H03M3/374 ,  H03M3/50

Abstract: This application relates to digital-to-analogue conversion with improved noise performance. Embodiments relate to digital-to-analogue conversion circuits (300) for converting a digital audio signal to an analogue audio signal having a digital-to-analogue converter (104) operable at a plurality of DAC clock rates. A first clock controller (301-1) controls the DAC clock rate based on an indication of the amplitude of the audio signal. The DAC clock rate (CK1) may be increased for low amplitude signal, where noise is important, to reduce the in-band thermal noise of the DAC. At higher amplitudes, when noise is less audible, the DAC clock rate may be reduced to avoid distortion. The amplitude of the audio signal may be monitored by a digital level detector (302) or in some cases by an analogue level detector (303). The DAC may be an oversampling DAC with an input interpolator (101) The conversion circuit may also include a word-length reduction module (102) and a dynamic error matching module (103) whose clock rates may also be varied based on the signal.

Abstract translation: 该应用涉及具有改进的噪声性能的数模转换。 实施例涉及用于将数字音频信号转换为模拟音频信号的数模转换电路（300），模拟音频信号具有可以多个DAC时钟速率工作的数模转换器（104）。 第一时钟控制器（301-1）基于音频信号的幅度的指示来控制DAC时钟速率。 对于噪声很重要的低幅度信号，DAC时钟频率（CK1）可能会增加，以降低DAC的带内热噪声。 在较高的幅度下，当噪声较小时，DAC时钟频率可能会降低，以避免失真。 音频信号的幅度可以由数字电平检测器（302）监视，或者在某些情况下由模拟电平检测器（303）监视。 DAC可以是具有输入内插器的过采样DAC（101）。转换电路还可以包括字长减小模块（102）和动态误差匹配模块（103），其时钟速率也可以基于该信号而变化。

公开(公告)号：US09019012B2

公开(公告)日：2015-04-28

申请号：US13677182

申请日：2012-11-14

Applicant: Wolfson Microelectronics plc

Inventor： John Paul Lesso

IPC: H03F3/217

CPC classification number: H03F3/217

Abstract: Methods and apparatus for Class-D amplifier circuits with D.C. offset control/correction. A Class-D amplifier is described having an output stage, such as a full H-bridge or half bridge, with a plurality of switches operable to provide a plurality of output states comprising at least a positive output state and a negative output state. Control circuitry is configured to receive a first signal based on the input signal and produce a digital control signal, which is used to determine the switch state of the output stage. A digital integrator is configured to receive a feedback signal indicative of the output state of the output stage and to sample the feedback signal at a sample rate and produce an integrated output signal (INT, IVC) indicating the difference in number of instances of the positive output state and the negative output state. Correction circuitry subtracts the integrated output signal from the input signal to produce a D.C. offset corrected signal.

Abstract translation: 具有D.C.偏移控制/校正的D类放大器电路的方法和装置。 描述了具有诸如全H桥或半桥的输出级的D类放大器，其中多个开关可操作以提供至少包括正输出状态和负输出状态的多个输出状态。 控制电路被配置为基于输入信号接收第一信号并产生用于确定输出级的开关状态的数字控制信号。 数字积分器被配置为接收指示输出级的输出状态的反馈信号，并以采样速率对反馈信号进行采样，并产生一个积分输出信号（INT，IVC），该信号表示正数的实例数 输出状态和负输出状态。 校正电路从输入信号中减去积分输出信号，产生D.C.偏移校正信号。

公开(公告)号：US20140159816A1

公开(公告)日：2014-06-12

申请号：US14182445

申请日：2014-02-18

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： John Paul Lesso

IPC: H03G3/00 ,  H03F3/185

CPC classification number: H03G3/3015 ,  H03F1/0216 ,  H03F1/0227 ,  H03F1/0261 ,  H03F1/30 ,  H03F3/185 ,  H03F3/193 ,  H03F2200/03 ,  H03F2200/504 ,  H03G3/001

Abstract: An amplifier circuit comprises an input, for receiving an input signal to be amplified; a preamplifier, for amplifying the input signal based on a variable gain; a power amplifier for amplifying the signal output from the preamplifier; and a variable voltage power supply for supplying one or more supply voltages to the power amplifier. The supply voltages are adjusted based on the variable gain or the input digital signal. According to other aspects of the invention, a power supply of an amplifier circuit is clocked using a clock signal, whereby the clock signal has a frequency that varies in accordance with a volume signal or an input signal.

Abstract translation: 放大器电路包括用于接收待放大的输入信号的输入端; 前置放大器，用于基于可变增益放大输入信号; 用于放大从前置放大器输出的信号的功率放大器; 以及用于向功率放大器提供一个或多个电源电压的可变电压电源。 电源电压根据可变增益或输入数字信号进行调整。 根据本发明的其他方面，使用时钟信号对放大器电路的电源进行定时，由此时钟信号具有根据音量信号或输入信号而变化的频率。