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公开(公告)号：US09716476B2
公开(公告)日：2017-07-25
申请号：US14142276
申请日：2013-12-27
Applicant: Wolfson Microelectronics plc
Inventor： John Paul Lesso
CPC classification number: H03F3/181 , H03F1/304 , H03F3/183 , H03F2200/03 , H03K3/013
Abstract: An apparatus and method for DC offset compensation. An amplifier receives an input signal (AIN) and provides an amplified output signal (SOUT) and a feedback path provides DC offset compensation. The feedback path comprises at least one voltage controlled oscillator (VCO) and a counter. The VCO provides, over time, a first VCO output signal based on said amplified output signal and a second VCO output signal based on a reference signal (VREF). The counter generates first pulse counts based upon the first VCO output signal and second pulse counts based upon the second VCO output signal and provides a compensation signal based on a comparison of the first and second pulse counts. One voltage controlled oscillator may sequentially receive a signal based on said amplifier output signal and the reference signal from a multiplexer so as to sequentially produce the first and second VCO output signals.
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公开(公告)号：US20150263686A1
公开(公告)日：2015-09-17
申请号：US14436648
申请日：2013-10-10
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： John Paul Lesso
CPC classification number: H03G3/001 , H03M1/0624 , H03M1/0626 , H03M1/0863 , H03M1/66 , H03M1/70
Abstract: The application relates to digital to analogue conversion circuits having dynamic gain control. A digital variable gain element (102) may apply gain to an input digital signal (DIN) upstream of a DAC (101) to make better use of the input range of the DAC and an analogue variable gain element (103) applies a compensating analogue gain. Again controller (201) has a gain allocation module (204) for controlling the allocation of gain between said digital and analogue variable gain elements in response to changes in a signal level of the input digital audio signal. In the present invention the gain allocation module is operable in first and second modes of operation where the response to reductions in signal level is slower in the first mode than in the second mode of operation. A low-level detector (202) monitors the input digital audio signal so as to detect a low-level part of the signal and the gain controller changes from the first mode to the second mode following detection of a low-level part of the input digital audio signal. The response of the gain allocation module in the second mode is preferably fast enough such that the digital gain can be changed to a target setting suitable for the low-level part of the signal before it is received at the digital gain element.
Abstract translation: 该应用涉及具有动态增益控制的数模转换电路。 数字可变增益元件（102）可以对DAC（101）上游的输入数字信号（DIN）施加增益，以更好地利用DAC的输入范围，并且模拟可变增益元件（103）应用补偿模拟 获得。 再次，控制器（201）具有增益分配模块（204），用于响应于输入数字音频信号的信号电平的变化来控制所述数字和模拟可变增益元件之间的增益分配。 在本发明中，增益分配模块可在第一和第二操作模式中操作，其中对第一模式的信号电平降低的响应比在第二操作模式中更慢。 低电平检测器（202）监视输入数字音频信号，以便在检测到输入的低电平部分之后检测信号的低电平部分，并且增益控制器从第一模式改变到第二模式 数字音频信号。 增益分配模块在第二模式中的响应优选地足够快，使得数字增益可以在其在数字增益元件被接收之前被改变为适合于信号的低电平部分的目标设置。
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公开(公告)号：US09281827B2
公开(公告)日：2016-03-08
申请号：US13678300
申请日：2012-11-15
Applicant: Wolfson Microelectronics plc
Inventor： John Paul Lesso
CPC classification number: H03L7/099 , G06F3/162 , H03G5/00 , H03G5/005 , H03L7/08 , H03L7/087 , H03L7/14 , H03L7/18 , H03L2207/50
Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.
Abstract translation: 时钟发生器接收第一和第二时钟信号，并且输入表示期望的频率比。 比较输出时钟信号和第一时钟信号的频率，第一误差信号表示期望频率比与该比较结果之间的差。 第一个错误信号被过滤。 比较输出时钟信号和第二时钟信号的频率，第二个误差信号表示滤波后的第一误差信号与该比较结果之间的差值。 第二个错误信号被过滤。 数字振荡器接收经滤波的第二误差信号并产生输出时钟信号。 结果，输出时钟信号在抖动频率的有用范围和第二输入时钟信号的频率精度上具有第一输入时钟信号的抖动特性。
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公开(公告)号：US20150039303A1
公开(公告)日：2015-02-05
申请号：US14314182
申请日：2014-06-25
Applicant: Wolfson Microelectronics plc
Inventor： John Paul Lesso , Robert James Hatfield
IPC: G10L15/20
CPC classification number: G10L15/20 , G10L15/28 , G10L17/24 , G10L21/0208 , G10L2015/088
Abstract: A speech recognition system comprises: an input, for receiving an input signal from at least one microphone; a first buffer, for storing the input signal; a noise reduction block, for receiving the input signal and generating a noise reduced input signal; a speech recognition engine, for receiving either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block; and a selection circuit for directing either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block to the speech recognition engine.
Abstract translation: 语音识别系统包括：用于接收来自至少一个麦克风的输入信号的输入; 第一缓冲器，用于存储输入信号; 降噪块，用于接收输入信号并产生降噪输入信号; 语音识别引擎，用于接收从第一缓冲器输出的输入信号或来自降噪块的降噪输入信号; 以及选择电路，用于将从第一缓冲器输出的输入信号或降噪输入信号从噪声降低块引导到语音识别引擎。
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公开(公告)号：US20130129114A1
公开(公告)日：2013-05-23
申请号：US13678300
申请日：2012-11-15
Applicant: Wolfson Microelectronics plc
Inventor： John Paul Lesso
CPC classification number: H03L7/099 , G06F3/162 , H03G5/00 , H03G5/005 , H03L7/08 , H03L7/087 , H03L7/14 , H03L7/18 , H03L2207/50
Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.
Abstract translation: 时钟发生器接收第一和第二时钟信号，并且输入表示期望的频率比。 比较输出时钟信号和第一时钟信号的频率，第一误差信号表示期望频率比与该比较结果之间的差。 第一个错误信号被过滤。 比较输出时钟信号和第二时钟信号的频率，第二个误差信号表示滤波后的第一误差信号与该比较结果之间的差值。 第二个错误信号被过滤。 数字振荡器接收经滤波的第二误差信号并产生输出时钟信号。 结果，输出时钟信号在抖动频率的有用范围和第二输入时钟信号的频率精度上具有第一输入时钟信号的抖动特性。
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Patent Agency Ranking
公开(公告)号：US20130127531A1
公开(公告)日：2013-05-23
申请号：US13677182
申请日：2012-11-14
Applicant: Wolfson Microelectronics plc
Inventor： John Paul Lesso
IPC: H03F3/217
CPC classification number: H03F3/217
Abstract: Methods and apparatus for Class-D amplifier circuits with D.C. offset control/correction. A Class-D amplifier is described having an output stage, such as a full H-bridge or half bridge, with a plurality of switches operable to provide a plurality of output states comprising at least a positive output state and a negative output state. Control circuitry is configured to receive a first signal based on the input signal and produce a digital control signal, which is used to determine the switch state of the output stage. A digital integrator is configured to receive a feedback signal indicative of the output state of the output stage and to sample the feedback signal at a sample rate and produce an integrated output signal (INT, IVC) indicating the difference in number of instances of the positive output state and the negative output state. Correction circuitry subtracts the integrated output signal from the input signal to produce a D.C. offset corrected signal.
Abstract translation: 具有D.C.偏移控制/校正的D类放大器电路的方法和装置。 描述了具有诸如全H桥或半桥的输出级的D类放大器，其中多个开关可操作以提供至少包括正输出状态和负输出状态的多个输出状态。 控制电路被配置为基于输入信号接收第一信号并产生用于确定输出级的开关状态的数字控制信号。 数字积分器被配置为接收指示输出级的输出状态的反馈信号，并以采样速率对反馈信号进行采样，并产生一个积分输出信号（INT，IVC），该信号表示正数的实例数 输出状态和负输出状态。 校正电路从输入信号中减去积分输出信号，产生D.C.偏移校正信号。
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公开(公告)号：US20150109056A1
公开(公告)日：2015-04-23
申请号：US14521191
申请日：2014-10-22
Applicant: Wolfson Microelectronics plc
Inventor： John Paul Lesso , Toru Ido
CPC classification number: H03F3/2171 , H03F1/0211 , H03F3/187 , H03F3/217 , H03F2200/165 , H03F2200/171 , H03F2200/333 , H03F2200/351 , H03G1/0088
Abstract: Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.
Abstract translation: 具有提高功率效率的D类放大器电路的方法和装置。 电路具有至少具有第一和第二开关的输出级和接收要被放大的输入信号SIN和第一时钟信号fSW的调制器。 调制器基于输入信号在开关周期内控制第一和第二开关的占空比，其中开关周期具有基于第一时钟信号的开关频率。 频率控制器响应于输入信号的幅度的指示来控制第一时钟信号的频率，以便提供第一输入信号幅度的第一开关频率和在第二输入信号幅度下的第二，较低开关频率 ，输入信号幅度。 在低信号幅度下可以容忍较低的开关频率，并且以这种方式改变开关频率，从而在降低开关功率损耗的同时保持稳定性。
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8.发明授权公开(公告)号：US08988149B2
公开(公告)日：2015-03-24
申请号：US13942303
申请日：2013-07-15
Applicant: Wolfson Microelectronics plc
Inventor： John Paul Lesso
CPC classification number: H03G3/3015 , H03F1/0216 , H03F1/0227 , H03F1/0261 , H03F1/30 , H03F3/185 , H03F3/193 , H03F2200/03 , H03F2200/504 , H03G3/001
Abstract: An amplifier circuit, comprising: an input, for receiving an input signal to be amplified; a power amplifier, for amplifying the input signal; a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switched power supply. The dither block is controlled based on the input signal. Another aspect of the invention involves using first and second switches, each having different capacitances and resistances, and using the first or second switch depending on the input signal or volume signal. Another aspect of the invention involves controlling a bias signal provided to one or more components in the signal path based on the input signal or volume signal.
Abstract translation: 一种放大器电路，包括：输入端，用于接收待放大的输入信号; 功率放大器，用于放大输入信号; 具有开关频率的开关电源，用于向所述功率放大器提供至少一个电源电压; 以及抖动块，用于使开关电源的开关频率抖动。 基于输入信号控制抖动块。 本发明的另一方面涉及使用具有不同电容和电阻的第一和第二开关，以及根据输入信号或音量信号使用第一或第二开关。 本发明的另一方面涉及基于输入信号或音量信号控制提供给信号路径中的一个或多个分量的偏置信号。
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公开(公告)号：US08957731B2
公开(公告)日：2015-02-17
申请号：US13677182
申请日：2012-11-14
Applicant: Wolfson Microelectronics plc
Inventor： John Paul Lesso
IPC: H03F3/217
Abstract: Methods and apparatus for Class-D amplifier circuits with D.C. offset control/correction. A Class-D amplifier is described having an output stage, such as a full H-bridge or half bridge, with a plurality of switches operable to provide a plurality of output states comprising at least a positive output state and a negative output state. Control circuitry is configured to receive a first signal based on the input signal and produce a digital control signal, which is used to determine the switch state of the output stage. A digital integrator is configured to receive a feedback signal indicative of the output state of the output stage and to sample the feedback signal at a sample rate and produce an integrated output signal (INT, IVC) indicating the difference in number of instances of the positive output state and the negative output state. Correction circuitry subtracts the integrated output signal from the input signal to produce a D.C. offset corrected signal.
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公开(公告)号：US08742970B2
公开(公告)日：2014-06-03
申请号：US13902638
申请日：2013-05-24
Applicant: Wolfson Microelectronics plc
Inventor： John Paul Lesso , John Laurence Pennock
CPC classification number: H03M1/00 , H03M1/1014 , H03M1/12 , H03M1/1225 , H03M1/186 , H03M1/34 , H03M1/60 , H03M2201/4233
Abstract: An apparatus and method for regulating analogue-to-digital converters. First and second input signals are received at controlled oscillator circuitry which generates respective first and second pulse streams with pulse rates based on the relevant input signal. Difference circuitry determines the difference in number of pulses of the first and second pulse streams and outputs a first digital signal. Circuitry also determines a signal independent value based on the number of pulses of the first and/or second pulse streams. In one embodiment this value is the sum or average of the number of pulses of the first and second pulse streams. This value can be used to calibrate for any variation in transfer characteristic of the oscillator circuitry. In one embodiment this value is compared to a reference value and a regulation signal passed to control circuitry to regulate the operation of the oscillation circuitry.
Abstract translation: 一种用于调节模数转换器的装置和方法。 在受控振荡器电路处接收第一和第二输入信号，该电路产生具有基于相关输入信号的脉冲速率的相应的第一和第二脉冲流。 差分电路确定第一和第二脉冲流的脉冲数的差异并输出第一数字信号。 电路还基于第一和/或第二脉冲流的脉冲数来确定与信号无关的值。 在一个实施例中，该值是第一和第二脉冲流的脉冲数的和或平均值。 该值可用于校准振荡器电路的传输特性的任何变化。 在一个实施例中，该值与参考值和传递给控制电路的调节信号进行比较以调节振荡电路的操作。
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