公开(公告)号：WO2022098396A1

公开(公告)日：2022-05-12

申请号：PCT/US2021/038842

申请日：2021-06-24

Applicant: XILINX, INC.

Inventor： CHIANG, Ping Chuan ,  RAJ, Mayank ,  XIE, Chuan ,  CHEN, Stanley Y. ,  KUMAR, Sandeep ,  PATTANAGIRI, Sukruth ,  UPADHYAYA, Parag ,  FRANS, Yohan

IPC: H04B10/80 ,  H04B10/69

Abstract: Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to- analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a sheer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the sheer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the sheer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the sheer circuit.

公开(公告)号：WO2022072027A1

公开(公告)日：2022-04-07

申请号：PCT/US2021/040696

申请日：2021-07-07

Applicant: XILINX, INC.

Inventor： POON, Chi Fung ,  LARABA, Asma ,  UPADHYAYA, Parag

IPC: H03K19/17796 ,  H01L23/552

Abstract: Examples described herein generally relate to communication between integrated circuit (1C) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (1C) die, a second 1C die, and a redistribution structure. The first 1C die includes a transmitter circuit. The second 1C die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single- ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.

公开(公告)号：WO2022066262A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/040600

申请日：2021-07-07

Applicant: XILINX, INC.

Inventor： RAJ, Mayank ,  UPADHYAYA, Parag

IPC: H03K19/0185 ,  H04B10/516 ,  H04B17/18

Abstract: Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.

公开(公告)号：WO2017209986A1

公开(公告)日：2017-12-07

申请号：PCT/US2017/033472

申请日：2017-05-19

Applicant: XILINX, INC.

Inventor： RAJ, Mayank ,  UPADHYAYA, Parag ,  BEKELE, Adebabay M.

IPC: H03L7/089 ,  H03L7/091

Abstract: An example a phase-locked loop (PLL) circuit (100) includes a sampling phase detector (103) configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump (107) configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter (109) configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) (1 16) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider (118) configured to generate the reference clock from the output clock.

Abstract translation: 一种锁相环（PLL）电路（100）的示例包括采样相位检测器（103），其被配置为接收参考时钟和反馈时钟并且被配置为提供第一控制电流和 脉冲信号。 PLL还包括电荷泵（107），电荷泵（107）被配置为基于第一控制电流和脉冲信号产生第二控制电流。 PLL还包括被配置为过滤第二控制电流并生成振荡器控制电压的环路滤波器（109）。 该PLL还包括被配置为基于该振荡器控制电压生成输出时钟的压控振荡器（VCO）（116）。 PLL还包括分频器（118），其被配置为从输出时钟生成参考时钟。

公开(公告)号：WO2017023529A1

公开(公告)日：2017-02-09

申请号：PCT/US2016/042853

申请日：2016-07-18

Applicant: XILINX, INC.

Inventor： RAJ, Mayank ,  UPADHYAYA, Parag

IPC: H03B5/12

CPC classification number: H03B5/124 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03B27/00 ,  H03B2200/0048 ,  H03B2200/0078

Abstract: A circuit for implementing a dual-mode oscillator is disclosed. The circuit comprises a first oscillator portion (204) having a first inductor (208) coupled in parallel with a first capacitor (210) between a first node (212) and a second node (214); a first pair of output nodes (293) coupled to the first and second nodes; a second oscillator portion (206) inductively coupled to the first oscillator portion, the second oscillator portion having a second inductor (258) coupled in parallel with a second capacitor (260) between a third node (262) and a fourth node (264); a second pair of output nodes (292) coupled to the third and fourth nodes; and a control circuit (207) coupled to enable a supply of current to either the first oscillator portion (204) or the second oscillator portion (206). A method of implementing a dual-mode oscillator is also disclosed.

Abstract translation: 公开了一种用于实现双模振荡器的电路。 该电路包括第一振荡器部分（204），其具有与第一电容器（210）并联耦合的第一电感器（208），位于第一节点（212）和第二节点（214）之间; 耦合到第一和第二节点的第一对输出节点（293）; 电感耦合到第一振荡器部分的第二振荡器部分（206），第二振荡器部分具有与第三节点（262）和第四节点（264）之间的第二电容器（260）并联耦合的第二电感器（258） ; 耦合到第三和第四节点的第二对输出节点（292）; 以及耦合到能够向第一振荡器部分（204）或第二振荡器部分（206）提供电流的控制电路（207）。 还公开了实现双模振荡器的方法。

公开(公告)号：WO2014055204A1

公开(公告)日：2014-04-10

申请号：PCT/US2013/058573

申请日：2013-09-06

Applicant: XILINX, INC.

Inventor： UPADHYAYA, Parag ,  SAVOJ, Jafar ,  TORZA, Anthony

IPC: H04L7/00 ,  H03L7/197 ,  H04J3/06 ,  H03M9/00

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/1976 ,  H04J3/0685 ,  H04L27/0014 ,  H04L2027/0059 ,  H04L2027/0067

Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder (290), at least one digital frequency mismatch number; decoding, with the at least one decoder (290), the at least one digital frequency mismatch number to obtain at least one digital frequency divider number (295) that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number (295) into at least one fractional-N phase lock loop (230); and utilizing, by the at least one fractional-N phase lock loop (230), the at least one digital frequency divider number (295) and an analog reference signal produced by a reference oscillator (250) to produce a resultant signal at the transmit frequency; wherein the at least one decoder (290) and the at least one fractional-N phase lock loop (230) are contained on a single field programmable gate array (280).

Abstract translation: 一种用于并行有线收发机的同步时钟生成方法，包括：向至少一个解码器（290）输入至少一个数字频率失配数; 使用所述至少一个解码器（290）解码所述至少一个数字频率失配数，以获得表示与至少一个信号相关联的发射频率的至少一个数字分频器数（295）; 将所述至少一个数字分频器编号（295）输入到至少一个小数N相锁定环（230）中; 以及由所述至少一个分数N锁相环（230）利用所述至少一个数字分频器编号（295）和由参考振荡器（250）产生的模拟参考信号，以在所述传输 频率; 其中所述至少一个解码器（290）和所述至少一个分数N相锁定环（230）被包含在单个现场可编程门阵列（280）上。

公开(公告)号：WO2023018460A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/029897

申请日：2022-05-18

Applicant: XILINX, INC.

Inventor： ZHANG, Wenfeng ,  UPADHYAYA, Parag

IPC: H03K5/24 ,  H04L25/06

Abstract: Receiver circuitry (122) for a communication system includes signal processing circuitry (213), voltage digital-to-analog converter (DAC) circuitry (229), and slicer circuitry (218, 220). The signal processing circuitry receives a data signal (130) and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage (235). The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage (235). The CapFF circuit further generates a first data signal (218out, 220out). The first CapFF circuit includes a first offset compensation circuit (223 or 225) that adjusts a parasitic capacitance of the first CapFF circuit.

公开(公告)号：WO2021183202A1

公开(公告)日：2021-09-16

申请号：PCT/US2020/067191

申请日：2020-12-28

Applicant: XILINX, INC.

Inventor： CHO, Junho ,  ZHENG, Kevin ,  UPADHYAYA, Parag

IPC: H03K19/017 ,  H03F1/42

Abstract: Electronic devices that include a continuous time linear equalizer, CTLE, are provided. An example of a CTLE includes a first inverter (402); a second inverter (404) having an input to receive an input signal (IN); a capacitor (408) coupled between an input of the first inverter (402) and the input of the second inverter (404); a resistor (410) coupled between a common-mode voltage (VCM) and the input of the first inverter; a third inverter (406) having an output to provide an output signal (Out); and a node (416) comprising an output of the first inverter (404), an output of the second inverter (402), an input of the third inverter (406), and the output of the third inverter.

公开(公告)号：WO2020180621A1

公开(公告)日：2020-09-10

申请号：PCT/US2020/020187

申请日：2020-02-27

Applicant: XILINX, INC.

Inventor： RAJ, Mayank ,  TURKER MELEK, Didem, Z. ,  UPADHYAYA, Parag ,  FRANS, Yohan ,  CHANG, Kun-Yung

IPC: H03L7/10 ,  H03L7/22 ,  H03L1/02 ,  H03L7/093 ,  H03L7/099

Abstract: A phase locked loop (PLL) circuit [ 200] includes a voltage controlled oscillator (VCO) [208], a first loop circuit [220], and a second loop circuit [222], The first loop circuit includes a first loop filter [206] configured to receive a first signal [224] based on a feedback signal [218] from the VCO and provide a first VCO frequency control signal [226] to the VCO. The second loop circuit includes a compensation circuit [210] configured to receive a reference signal [218] and the first signal, and provide a second VCO frequency control signal [228] to the VCO.

公开(公告)号：WO2018013241A1

公开(公告)日：2018-01-18

申请号：PCT/US2017/035236

申请日：2017-05-31

Applicant: XILINX, INC.

Inventor： NAMKOONG, Jinyung ,  RAJ, Mayank ,  UPADHYAYA, Parag ,  MANTHENA, Vamshi ,  HEARNE, Catherine ,  ERETT, Marc

IPC: H03L7/099 ,  H03L7/24 ,  H03L7/08

Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit (100) includes an injection locked oscillator (102), a loop controller (116), and a phase interpolator (108). The injection locked oscillator (102) includes an input for receiving an injected clock signal (112) and an output for forwarding a set of fixed clock phases. The loop controller (116) includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator (102) to a frequency of the injected clock signal (112). The phase interpolator (108) includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator (102), an input for receiving the supply voltage from the loop controller (116), and an output for forwarding an arbitrary clock phase.

Abstract translation: 公开了一种用于时钟相位产生的方法，非暂时性计算机可读介质和电路。 电路（100）包括注入锁定振荡器（102），回路控制器（116）和相位内插器（108）。 注入锁定振荡器（102）包括用于接收注入时钟信号（112）的输入端和用于转发一组固定时钟相位的输出端。 环路控制器（116）包括用于接收固定时钟相位的相位分离误差的输入端和用于转发源自相位分离误差的电源电压的输出端。 电源电压将注入锁定振荡器（102）的自由运行频率与注入的时钟信号（112）的频率相匹配。 相位插值器（108）包括一个用于直接从注入锁定振荡器（102）接收一组固定时钟相位的输入端，一个用于接收来自环路控制器（116）的电源电压的输入端和一个用于转发任意时钟 相。