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    PLESIOCHRONOUS CLOCK GENERATION FOR PARALLEL WIRELINE TRANSCEIVERS
    1.
    发明申请
    PLESIOCHRONOUS CLOCK GENERATION FOR PARALLEL WIRELINE TRANSCEIVERS 审中-公开
    平行线路收发器的时钟产生

    公开(公告)号：WO2014055204A1

    公开(公告)日：2014-04-10

    申请号：PCT/US2013/058573

    申请日：2013-09-06

    Applicant: XILINX, INC.

    Inventor： UPADHYAYA, Parag ,  SAVOJ, Jafar ,  TORZA, Anthony

    IPC: H04L7/00 ,  H03L7/197 ,  H04J3/06 ,  H03M9/00

    CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/1976 ,  H04J3/0685 ,  H04L27/0014 ,  H04L2027/0059 ,  H04L2027/0067

    Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder (290), at least one digital frequency mismatch number; decoding, with the at least one decoder (290), the at least one digital frequency mismatch number to obtain at least one digital frequency divider number (295) that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number (295) into at least one fractional-N phase lock loop (230); and utilizing, by the at least one fractional-N phase lock loop (230), the at least one digital frequency divider number (295) and an analog reference signal produced by a reference oscillator (250) to produce a resultant signal at the transmit frequency; wherein the at least one decoder (290) and the at least one fractional-N phase lock loop (230) are contained on a single field programmable gate array (280).

    Abstract translation: 一种用于并行有线收发机的同步时钟生成方法，包括：向至少一个解码器（290）输入至少一个数字频率失配数; 使用所述至少一个解码器（290）解码所述至少一个数字频率失配数，以获得表示与至少一个信号相关联的发射频率的至少一个数字分频器数（295）; 将所述至少一个数字分频器编号（295）输入到至少一个小数N相锁定环（230）中; 以及由所述至少一个分数N锁相环（230）利用所述至少一个数字分频器编号（295）和由参考振荡器（250）产生的模拟参考信号，以在所述传输 频率; 其中所述至少一个解码器（290）和所述至少一个分数N相锁定环（230）被包含在单个现场可编程门阵列（280）上。

    DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT
    2.
    发明申请
    DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT 审中-公开
    数据接收器和在集成电路中实现数据接收器的方法

    公开(公告)号：WO2015094865A1

    公开(公告)日：2015-06-25

    申请号：PCT/US2014/069608

    申请日：2014-12-10

    Applicant: XILINX, INC.

    Inventor： HSIEH, Cheng-Hsiang ,  CHANG, Kun-Yung ,  SAVOJ, Jafar

    IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

    CPC classification number: H04L7/0025 ,  H04L7/0062 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/03057 ,  H04L25/03885

    Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input (305) receiving a data signal; a first equalization circuit (304) coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit (310) coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

    Abstract translation: 描述了在集成电路中实现的数据接收器。 数据接收机包括接收数据信号的输入端（305） 耦合以接收所述数据信号的第一均衡电路（304），其中所述第一均衡电路用于接收所述数据信号的数据; 以及耦合以接收所述数据信号的第二均衡电路（310），其中所述第二均衡电路用于调整时钟相位偏移。

    RECEIVER HAVING A WIDE COMMON MODE INPUT RANGE
    3.
    发明申请
    RECEIVER HAVING A WIDE COMMON MODE INPUT RANGE 审中-公开
    接收器具有宽共通模式输入范围

    公开(公告)号：WO2014018124A1

    公开(公告)日：2014-01-30

    申请号：PCT/US2013/033381

    申请日：2013-03-21

    Applicant: XILINX, INC.

    Inventor： LIM, Siok, Wei ,  HSIEH, Cheng-hsiang ,  SAVOJ, Jafar

    IPC: H03F3/45 ,  H03F1/52 ,  H03F3/72

    CPC classification number: H03F1/523 ,  H03F3/45224 ,  H03F3/45233 ,  H03F3/72 ,  H03F2200/444 ,  H03F2203/45091 ,  H03F2203/45092 ,  H03F2203/45466 ,  H03F2203/45494 ,  H03F2203/45568 ,  H03H11/1213 ,  H04L25/0276 ,  H04L27/0002

    Abstract: In one embodiment, a differential amplifier (130) is provided. Gates of a first differential pair of transistors (132/134), of a first conductivity type, and a second pair or transistors (146/148), of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources (136/138) are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources (152/154) are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources (142/144) are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

    Abstract translation: 在一个实施例中，提供了差分放大器（130）。 具有第二导电类型的第一导电类型的第一差分对晶体管（132/134）和第二对晶体管（146/148）的栅极耦合到差分放大器的第一和第二输入端。 第一对可调电流源（136/138）被配置为响应于第一偏置电流控制信号来调整第一差分对晶体管的相应尾电流。 第二对可调电流源（152/154）被配置为响应于第一偏置电流控制信号来调整第二差分对晶体管的相应尾电流。 第三对可调电流源（142/144）被配置为响应于第二偏置电流控制信号来调节通过第二差分对晶体管的相应电流。

    RECEIVER HAVING A WIDE COMMON MODE INPUT RANGE
    4.
    发明公开
    RECEIVER HAVING A WIDE COMMON MODE INPUT RANGE 有权
    EMPFÄNGERMIT GROSSEM GLEICHTAKT-EINGANGSSIGNALUMFANG

    公开(公告)号：EP2878079A1

    公开(公告)日：2015-06-03

    申请号：EP13716561.9

    申请日：2013-03-21

    Applicant: Xilinx, Inc.

    Inventor： LIM, Siok, Wei ,  HSIEH, Cheng-hsiang ,  SAVOJ, Jafar

    IPC: H03F3/45 ,  H03F1/52 ,  H03F3/72

    CPC classification number: H03F1/523 ,  H03F3/45224 ,  H03F3/45233 ,  H03F3/72 ,  H03F2200/444 ,  H03F2203/45091 ,  H03F2203/45092 ,  H03F2203/45466 ,  H03F2203/45494 ,  H03F2203/45568 ,  H03H11/1213 ,  H04L25/0276 ,  H04L27/0002

    Abstract: In one embodiment, a differential amplifier (130) is provided. Gates of a first differential pair of transistors (132/134), of a first conductivity type, and a second pair or transistors (146/148), of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources (136/138) are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources (152/154) are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources (142/144) are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

    Abstract translation: 在一个实施例中，提供了差分放大器。 具有第二导电类型的第一导电类型和第二对晶体管的第一差分对晶体管的栅极耦合到差分放大器的第一和第二输入端。 第一对可调电流源被配置为响应于第一偏置电流控制信号来调整第一差分对晶体管的相应尾电流。 第二对可调电流源被配置为响应于第一偏置电流控制信号来调整第二差分对晶体管的相应尾电流。 第三对可调电流源被配置为响应于第二偏置电流控制信号来调节通过第二差分对晶体管的相应电流。

    DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT
    7.
    发明公开
    DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT 有权
    接收器和方法履行数据接收机在集成电路

    公开(公告)号：EP3085003A1

    公开(公告)日：2016-10-26

    申请号：EP14824648.1

    申请日：2014-12-10

    Applicant: Xilinx, Inc.

    Inventor： HSIEH, Cheng-Hsiang ,  CHANG, Kun-Yung ,  SAVOJ, Jafar

    IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

    CPC classification number: H04L7/0025 ,  H04L7/0062 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/03057 ,  H04L25/03885

    Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input (305) receiving a data signal; a first equalization circuit (304) coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit (310) coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

    Abstract translation: 上的集成电路中实现的数据接收器进行说明。 数据接收器输入接收的数据信号的步骤包括; 耦合以接收所述数据信号，worin第一均衡电路的第一均衡电路用于接收所述数据信号的所述数据; 和耦合以接收所述数据信号，worin第二均衡电路的第二均衡电路用于调整时钟相位偏移。

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