公开(公告)号：JPH10104282A

公开(公告)日：1998-04-24

申请号：JP15138597

申请日：1997-06-09

Applicant: YAMAHA CORP

Inventor： SHICHIMIYA TAKATOMO ,  TANAKA TAISHIN

IPC: G01R19/165 ,  G05F1/56 ,  G05F3/24 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable exhibiting a desired function independently from a power source voltage by switching the number of MOSFETs to be driven on the basis of the detection result of a supplied power source voltage. SOLUTION: In a power source voltage detecting circuit, a signal of high level is outputted from a node S1 when the power source voltage of an IC is lower than a prescribed value, and a signal of low level is outputted when it is higher. A plurality of MOSFETs are connected in parallel. When the low- level signal is outputted from the node S1, one MOSFET is forcedly brought to the off-state, and only the other MOSFET is used. When the high-level signal is conversely outputted, both the MOSFETs are used. Thus, since the number of MOSFETs to be operated can be increased to carry a sufficient driving power to the load of the MOSFETs, even if the supplied power source voltage is reduced, a semiconductor integrated circuit can exhibit a desired function independently from the power source voltage.

公开(公告)号：JPH08335397A

公开(公告)日：1996-12-17

申请号：JP16301095

申请日：1995-06-06

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C17/18 ,  G11C16/02

Abstract: PURPOSE: To provide a semiconductor memory of a clock synchronizing system having a chip selecting function which can surely output data. CONSTITUTION: In a mask ROM provided with a memory cell array 1, an address buffer 2, a row decoder 3, a column selector 4, a sense amplifier 5, and an output circuit 6, the address buffer 2, the row decoder 3, the sense amplifier 5, and the output circuit 6 are made a clock synchronizing system. Activation and non-activation of the address buffer 2, the row decoder 3, the sense amplifier 5, and the output circuit 6 are controlled by providing a shift register 8 which generates internal activation signals /CSa, /CSb, /CSc, /CSd of which each phase is delayed by one clock cycle successively.

公开(公告)号：JPH0855491A

公开(公告)日：1996-02-27

申请号：JP19261894

申请日：1994-08-16

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C17/12

Abstract: PURPOSE:To make signal amplitude small and to output high speed data by varying first and second signals in comple-mentary relation in accordance with data stored in a ROM. CONSTITUTION:Memory cells M01, M02 selected by word lines W1, W2 are transistors HiVt, LoVt respectively. And when a bit line select-signal BS0 and a line W1 are made H and the cell M01 is selected, a bit data BD level is made lower than the reference data Ref. Also, when a signal BS0 and a line W2 are made H and the cell MO2 is selected, a bit data BD level is made higher than the reference data Ref. When a cell is M01, data BD, Ref are not varied from pre-charge to read-out, even instantaneous read-out can be performed in a stable level. On the other hand, when a cell is M02, levels of data BD, Ref are reversed approaching each other, and data inversion can be performed at high speed. Therefore, data can be read out form a cell at high speed.

公开(公告)号：JPH07334998A

公开(公告)日：1995-12-22

申请号：JP15163394

申请日：1994-06-09

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C17/18 ,  G11C16/06

Abstract: PURPOSE:To improve the high speed performance and noise resistance by constituting a data sense circuit by using a clock synchronization type sense amplifier of two systems operating in time-division mode. CONSTITUTION:Address data is fetched in address latches 111a, 111b of two systems alternately in time-division made at falling timing of a clock CK, and alternately selected by a selector 12 at rising timing of the CK and taken out. A word line and a bit line of a memory cell array 101 are selected by an address taken out by the selector 112. Bit line data is alternately read out by sense amplifiers 113a, 113b of two systems in time-division mode at rising timing of the CK, and alternately selected by the selector 114 and outputted. Thereby, during one side of sense amplifiers outputs data, the other sense amplifier reads out data of the next cycle, and the high speed performance and noise resistance can be improved.

公开(公告)号：JP2010278697A

公开(公告)日：2010-12-09

申请号：JP2009128433

申请日：2009-05-28

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： SASAKI KOSUKE ,  TANAKA TAISHIN

IPC: H03F1/00 ,  H03F3/217

Abstract: PROBLEM TO BE SOLVED: To reduce pop noise in a class D amplifier.
SOLUTION: A reproducing device 1A includes: a first driving circuit 12 for supplying a first output signal OUTP obtained by performing class D amplification of a first pulsewidth modulation signal 11a to one input terminal of a lowpass filter 20; a second driving circuit 13 for supplying a second output signal OUTN obtained by performing class D amplification of a second pulsewidth modulation signal 11b to the other input terminal of the lowpass filter 20; and a delay circuit 40 for delaying the first output signal OUTP only for a predetermined time to generate a control signal CTL and performing control to stop output of the first output signal OUTP and the second output signal OUTN when a mute signal MUTE is supplied from the outside.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：减少D类放大器中的流行噪声。 解决方案：再现装置1A包括：第一驱动电路12，用于将通过对第一脉宽调制信号11a进行D类放大获得的第一输​​出信号OUTP提供给低通滤波器20的一个输入端; 第二驱动电路13，用于将通过对第二脉冲宽度调制信号11b进行D类放大而获得的第二输出信号OUTN提供给低通滤波器20的另一输入端; 以及延迟电路40，用于仅延迟预定时间的第一输出信号OUTP以产生控制信号CTL，并且当从所述第一输出信号MUTP提供静音信号MUTE时执行控制以停止第一输出信号OUTP和第二输出信号OUTN的输出 外。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009021903A

公开(公告)日：2009-01-29

申请号：JP2007184006

申请日：2007-07-13

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAI HIROKATA ,  TSUJI NOBUAKI ,  TANAKA TAISHIN

IPC: H03F3/217

CPC classification number: H03F3/2173 ,  H03F2200/03 ,  H03F2200/351

Abstract: PROBLEM TO BE SOLVED: To achieve reduction of distortion and reduction of power loss when inputting a fine signal in a class D amplifier circuit. SOLUTION: A pulse monitor circuit 60 detects the presence or non-presence of the output pulses outputted from an output stage circuit 40. The pulse monitor circuit outputs an up signal to an up/down counter 70 when the output pulses do not exist at all and outputs a down signal to the up/down counter 70 when the output pulses exist. The up/down counter 70 outputs a signal for increasing the delay amount of a delay amount variable circuit 50 when a count value is large, that is, when the output pulses disappear. In contrast, when the count value is small, that is, when the output pulses exist, the counter outputs the signal for reducing the delay amount of the delay amount variable circuit 50. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：当在D类放大器电路中输入精细信号时，实现失真的减小和功率损耗的降低。

解决方案：脉冲监视电路60检测从输出级电路40输出的输出脉冲的存在或不存在。当输出脉冲不是时，脉冲监视电路向上/向下计数器70输出上升信号 完全存在，并且当存在输出脉冲时，向加/减计数器70输出下降信号。 当计数值较大时，即输出脉冲消失时，升降计数器70输出用于增加延迟量可变电路50的延迟量的信号。 相反，当计数值小时，即当存在输出脉冲时，计数器输出用于减小延迟量可变电路50的延迟量的信号。（C）2009，JPO＆INPIT

公开(公告)号：JP2008017367A

公开(公告)日：2008-01-24

申请号：JP2006188713

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  TSUJI NOBUAKI ,  KAWAI HIROKATA

IPC: H03G3/30 ,  H03G3/20

Abstract: PROBLEM TO BE SOLVED: To provide an automatic gain control circuit (AGC circuit) capable of properly setting its attack time and its release time without provision of an externally mounted time constant circuit.
SOLUTION: A control section 100 executes control of increasing a reference level Vr in matching with an increase in input audio signals LIN and RIN at rising of a base clock BCK, executes control of decreasing the reference level Vr in matching with a decrease in the input audio signals LIN and RIN when a base clock BCK_N and a release clock RLSCK_N both go to an L level, and executes control of decreasing or increasing gain of each of electronic volumes so as to reach a gain correlated with the reference level Vr at the rising of an attack clock ATKCK.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够在不设置外部安装的时间常数电路的情况下适当地设定其启动时间和释放时间的自动增益控制电路（AGC电路）。 解决方案：控制部分100在基本时钟BCK的上升时执行与输入音频信号LIN和RIN的增加相匹配的增加参考电平Vr的控制，执行降低参考电平Vr的控制以与减小相匹配 当基本时钟BCK_N和释放时钟RLSCK_N都变为L电平时，在输入音频信号LIN和RIN中，执行降低或增加每个电子体积的增益的控制，以达到与参考电平Vr相关的增益 在攻击时钟ATKCK的上升。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008017358A

公开(公告)日：2008-01-24

申请号：JP2006188657

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  TSUJI NOBUAKI ,  KAWAI HIROKATA

IPC: H03F3/34 ,  H03F3/217 ,  H03F3/26

Abstract: PROBLEM TO BE SOLVED: To provide a class-D amplifier capable of correcting offset voltage caused by the difference in the resistance value constituting the class-D amplifier.
SOLUTION: The class-D amplifier comprises an input means for inputting an input signal; an integration means that comprises a differential operational amplifier, having an offset voltage correction functions and integrates the input signal inputted via the input means; a modulation means for generating a pulse signal, where a result integrated by the integration means is subjected to pulse width modulation and the integrated result is reflected on pulse width; an output means for outputting the pulse signal; a feedback means for making the output signal of the output means superimpose on the input signal for feeding back to the integration means; an input control means for setting the input means to be a signal absence input state; and an output control means for setting the voltage of the output signal of the output means to voltage to be fed back by the feedback means in the signal absense input state.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供能够校正由构成D类放大器的电阻值的差引起的偏移电压的D类放大器。 解决方案：D类放大器包括用于输入输入信号的输入装置; 积分装置，包括具有偏移电压校正功能的差分运算放大器，并且对通过输入装置输入的输入信号进行积分; 用于产生脉冲信号的调制装置，其中由积分装置积分的结果经受脉冲宽度调制，积分结果反映在脉冲宽度上; 用于输出脉冲信号的输出装置; 用于使输出装置的输出信号叠加在输入信号上以反馈到积分装置的反馈装置; 输入控制装置，用于将输入装置设置为无信号输入状态; 以及输出控制装置，用于将输出装置的输出信号的电压设置为由反馈装置在信号缺失输入状态下反馈的电压。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008017353A

公开(公告)日：2008-01-24

申请号：JP2006188623

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TSUJI NOBUAKI ,  TANAKA TAISHIN ,  KAWAI HIROKATA

IPC: H03F1/52 ,  H03F3/217

Abstract: PROBLEM TO BE SOLVED: To provide a class-D amplifier which includes a function for detecting a DC output in simple configuration and can prevent the DC output from being applied to a speaker.
SOLUTION: The present invention relates to the class-D amplifier configured to perform pulse width modulation on an analog input signal and to generate and output first and second pulse signals of which a duty complementarily changes in accordance with a signal level of the analog input signal, and comprising: a signal converting section (151) in which the first and second pulse signals are inputted to SC and SD and converted into first and second signals which become a predetermined level complementarily in accordance with the signal level of the analog input signal; and a clocking section (152) for detecting that any one of the first and second signals maintains the predetermined level for a predetermined time.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种D类放大器，其包括用于以简单配置检测DC输出的功能，并且可以防止DC输出被施加到扬声器。 解决方案：本发明涉及被配置为对模拟输入信号执行脉冲宽度调制的D类放大器，并且根据信号电平产生和输出占空比互补地改变的第一和第二脉冲信号 模拟输入信号，并且包括：信号转换部（151），其中第一和第二脉冲信号被输入到SC和SD，并且根据模拟信号的信号电平被转换成成为预定电平的第一和第二信号 输入信号 以及用于检测第一和第二信号中的任何一个在预定时间内保持预定电平的计时部分（152）。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004259444A

公开(公告)日：2004-09-16

申请号：JP2004176038

申请日：2004-06-14

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN

IPC: G11C11/409

Abstract: PROBLEM TO BE SOLVED: To efficiently perform data reading/writing (refresh) by eliminating special duration for pre-charge.
SOLUTION: The reading/writing circuit of memory cells comprises: the memory cells which store electric charge so as to correspond to the level of a bit line Bit through instructions from writing words WWrd in a writing mode and transits the level of the bit line Bit in accordance with the stored electric charge through instructions from reading word lines RWrd in a reading mode; and a transistor 11 which connects the bit line Bit to a power supply voltage Vdd in the reading mode. In addition, the reading/writing circuit of the memory cells comprises: an inverter 12 which reads the data written on the memory cells depending on whether the level of the bit line Bit is transited from pull-up level or not in the reading mode; and an inverter 15 which selects read data or data to be newly written through a selector 14 and transits the level of the bit line Bit to the corresponding level in the writing mode.
COPYRIGHT: (C)2004,JPO&NCIPI