公开(公告)号：JP2011049345A

公开(公告)日：2011-03-10

申请号：JP2009196252

申请日：2009-08-27

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  YAMAZAKI YASUHIRO ,  SUZUKI MASAYA

IPC: H01L27/04 ,  H01L21/822 ,  H03K19/003 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide an ESD protection circuit using an output buffer, capable of protecting satisfactorily a prestage circuit such as a prebuffer, without providing a dedicated element for making a surge current flow when applying an ESD surge.
SOLUTION: The ESD protection circuit includes: the prebuffer 10 operated in response to an input signal IN; an output buffer 20 with an electric power source shared with the prebuffer 10, and operated based on an output from the prebuffer 10, to drive a load; and a protection function-effectuating circuit 30, operated when applying the ESD surge to the electric power source, and for turning the output buffer 20 on, to absorb the surge current by the output buffer.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了提供使用输出缓冲器的ESD保护电路，能够令人满意地保护诸如预缓冲器的预置电路，而不需要在施加ESD浪涌时提供用于产生浪涌电流的专用元件。 解决方案：ESD保护电路包括：预缓冲器10响应于输入信号IN而操作; 输出缓冲器20，其具有与预缓冲器10共用的电源，并且基于来自预缓冲器10的输出进行操作以驱动负载; 以及保护功能实现电路30，其在将ESD浪涌施加到电源时操作，并且用于使输出缓冲器20接通，以便通过输出缓冲器吸收浪涌电流。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008028446A

公开(公告)日：2008-02-07

申请号：JP2006195578

申请日：2006-07-18

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  TSUJI NOBUAKI ,  KAWAI HIROKATA

IPC: H03F3/34 ,  H03F1/34 ,  H03G3/30 ,  H03K17/687

Abstract: PROBLEM TO BE SOLVED: To provide a highly precise pull-up/pull-down circuit capable of highly precisely matching a pul-up current and a pull-down current with each other in their values.
SOLUTION: The highly precise pull-up/pull-down circuit 1 comprises P-channel transistors TP1, TP2, N-channel transistors TN1, TN2, a reference voltage source 11, and a control circuit 12. The control circuit 12 adopts a configuration of an operational amplifier circuit, a voltage Vref at nodes NA, NB is given to a negative (-) input terminal, and the feedback configuration controls a voltage at a connecting point (point C) between the P-channel transistor TP2 and the N-channel transistor TN2 to be equal to the voltage Vref. In this case, since a current Ipuo is equal to a current Ipd and the current Ipuo is accurately mirrored to the current Ipd and the current Ipdo is accurately mirrored to the current Ipd, the circuit 1 can match the pull-up current Ipu and the pull-down current Ipd with each other in their values highly precisely.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种高精度的上拉/下拉电路，其能够将其上升的电流和下拉电流高精度地匹配在其值中。 解决方案：高精度上拉/下拉电路1包括P沟道晶体管TP1，TP2，N沟道晶体管TN1，TN2，参考电压源11和控制电路12.控制电路12 采用运算放大电路的结构，将节点NA，NB的电压Vref提供给负（ - ）输入端，反馈结构控制P沟道晶体管TP2之间的连接点（C点）处的电压 并且N沟道晶体管TN2等于电压Vref。 在这种情况下，由于电流Ipuo等于电流Ipd，并且电流Ipuo被精确地反映到电流Ipd，并且电流Ipdo被精确地反映到电流Ipd，所以电路1可匹配上拉电流Ipu和 下拉电流Ipd以其精确度高估其值。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008017319A

公开(公告)日：2008-01-24

申请号：JP2006188302

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAI HIROKATA ,  TSUJI NOBUAKI ,  TANAKA TAISHIN

IPC: H03G11/00

Abstract: PROBLEM TO BE SOLVED: To achieve such limiter characteristics that unwanted waveform deformation does not occur. SOLUTION: A differential amplifier circuit included in a limiter circuit 10 amplifies a potential difference between a control voltage and the potential of an input signal and outputs the amplified potential difference. When the potential of the input signal exceeds the potential level of a limit voltage, current is supplied to a resistor 1 and the potential level of a node N1 is controlled not to exceed the limit voltage. Since the potential difference appears in an amplified state by using the differential amplifier circuit, when the potential of the input signal exceeds the potential level of the limit voltage, a switching element (such as an NMOS transistor 5 or a PMOS transistor 6) is speedily turned on and the current can flow to the resistor 1. Namely, ON/OFF of operation of the switching element can be accurately changed over, then, excellent limiter characteristics can be materialized. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了实现不发生不需要的波形变形的这种限制器特性。 解决方案：限幅器电路10中包括的差分放大器电路放大控制电压和输入信号的电位之间的电位差，并输出放大的电位差。 当输入信号的电位超过极限电压的电位时，电流被提供给电阻器1，并且节点N1的电位电平被控制为不超过极限电压。 由于通过使用差分放大器电路在放大状态下出现电位差，所以当输入信号的电位超过极限电压的电位时，开关元件（例如NMOS晶体管5或PMOS晶体管6）迅速地 导通并且电流可以流到电阻器1.即，可以精确地切换开关元件的操作的ON / OFF，从而可以实现优异的限制器特性。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008017310A

公开(公告)日：2008-01-24

申请号：JP2006188197

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAI HIROKATA ,  TSUJI NOBUAKI ,  TANAKA TAISHIN

IPC: H03F3/217

Abstract: PROBLEM TO BE SOLVED: To prevent a class D amplification circuit from clipping for a technique for performing class D amplification.
SOLUTION: First and second pulse width modulation signals Pa and Pb are fed back to an operational amplification section 10 via a low-pass filter 20 as feedback signals FBa and FBb. The operational amplification section 10 composites input signals Vin+ and Vin- and the feedback signals FBa and FBb each, performs secondary integration, and generates an integral signal X. A PWM signal generation section 40 generates the first and second pulse width modulation signals Pa and Pb, based on the comparison result between a triangular signal TRI and the integral signal X.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了防止D类放大电路对于用于执行D类放大的技术的限幅。 解决方案：第一和第二脉冲宽度调制信号Pa和Pb作为反馈信号FBa和FBb经由低通滤波器20反馈到操作放大部分10。 操作放大部分10将输入信号Vin +和Vin-以及反馈信号FBa和FBb各自进行二次积分，并产生积分信号X. PWM信号产生部分40产生第一和第二脉冲宽度调制信号Pa和Pb ，基于三角形信号TRI和积分信号X之间的比较结果。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004056211A

公开(公告)日：2004-02-19

申请号：JP2002207226

申请日：2002-07-16

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  NORO MASAO

IPC: H03K17/687 ,  H03F3/217 ,  H03F3/30

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of configuring a drive circuit for almost simultaneously switching a plurality of power MOS transistors provided in parallel connection at the output stage of a class-D amplifier.
SOLUTION: A non-inverting pulse signal and an inverting pulse signal that are PWM-modulated inside the class D amplifier are applied to first and second input terminals. Input parts of a comparator are connected to the first and second input terminals, an output part of the comparator is connected to a first output terminal, an input part of a buffer is connected to a third input terminal, and its output part is connected to a second output terminal. Any gate of a plurality of the power MOS transistors provided in parallel connection to the output stage of the class D amplifier is connected to the second output terminal. The drive circuit is configured by using semiconductor devices 303H to 303HC, and 303LA to 303LC with the configuration above.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种能够构成用于在D类放大器的输出级几乎同时切换并联连接的多个功率MOS晶体管的驱动电路的半导体器件。 解决方案：在D类放大器内进行PWM调制的非反相脉冲信号和反相脉冲信号被施加到第一和第二输入端。 比较器的输入部分连接到第一和第二输入端子，比较器的输出部分连接到第一输出端子，缓冲器的输入部分连接到第三输入端子，其输出部分连接到 第二输出端子。 与D类放大器的输出级并联设置的多个功率MOS晶体管的任意一个栅极与第二输出端子连接。 通过使用具有上述结构的半导体器件303H至303HC和303LA至303LC来配置驱动电路。 版权所有（C）2004，JPO

公开(公告)号：JPH10199256A

公开(公告)日：1998-07-31

申请号：JP35045096

申请日：1996-12-27

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C11/41 ,  H03K5/1532

Abstract: PROBLEM TO BE SOLVED: To provide a signal change detecting circuit which is useful as an address transition detecting circuit which can independently set the optimum values of the widths of a rising edge detecting signal and a falling edge detecting signal of a pulse signal. SOLUTION: A first delay circuit 11 for producing a first delay pulse signal N1 obtained by delaying the rising edge of an address pulse signal AD and a second delay circuit 12 for producing a second delay pulse N3 obtained by delaying the falling edge of the address pulse signal AD are provided in combination. The delay circuits 11, 12 adjust amount of delay with given DC biases VCR, VCF. The first delay pulse signal N1 and address pulse signal AD are input to a first EOR gate 13 to obtain the rising edge detecting signal N2. The second delay pulse signal N3 and address pulse signal AD are input to a second EOR gate 14 to obtain the falling edge detecting signal N4. These detecting signals N2, N4 are combined with an OR gate 15 to obtain an ATD (Address Transition Detecting Circuit) signal.

公开(公告)号：JP2012231224A

公开(公告)日：2012-11-22

申请号：JP2011097059

申请日：2011-04-25

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： HASHIMOTO YUYA ,  TANAKA TAISHIN ,  MITSUOKA KUNIHIKO

IPC: H03F1/52 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To be able to directly detect damage to an element being monitored.SOLUTION: Monitoring wiring is installed in the vicinity of a semiconductor element being monitored. Clock output means for outputting a predetermined clock is connected to one end of the monitoring wiring, and monitoring means is connected to the other end of the monitoring wiring. The monitoring means is caused to monitor propagation of the clock output from the clock output means to the monitoring wiring. When it is detected that propagation of the clock has ceased, the monitoring means is caused to output a damage notification signal notifying that the semiconductor element being monitored has been damaged.

Abstract translation: 要解决的问题：能够直接检测被监测元件的损坏。

解决方案：监控接线安装在被监测的半导体元件附近。 用于输出预定时钟的时钟输出装置连接到监视配线的一端，并且监视装置连接到监控配线的另一端。 使监视装置监视从时钟输出装置输出的时钟到监视布线的传播。 当检测到时钟的传播已经停止时，使监视装置输出通知被监视的半导体元件已被损坏的损坏通知信号。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2008021088A

公开(公告)日：2008-01-31

申请号：JP2006191630

申请日：2006-07-12

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TSUJI NOBUAKI ,  TANAKA TAISHIN ,  KAWAI HIROKATA

IPC: G05F3/24 ,  G11C11/4074 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit maintaining stable operation even if voltage Vt required for turning on a transistor constituting a start-up circuit is relatively high. SOLUTION: In the reference voltage generating circuit, potential of a node N5 is input into a gate of an NMOS transistor 33 included in the start-up circuit 30a simultaneously with power-on. The potential of the node N5 becomes higher than an output node N1 by potential difference generated by a resistor 43. Therefore, when the value of the resistor 43 is set so as to exceed Vt of the NMOS transistor 33 before the potential of the output node N1 becomes an essential reference voltage, even if the Vt of the transistor 33 constituting the start-up circuit is relatively high, the reference voltage generating circuit does not output voltage exceeding the reference voltage, and can promptly start and stably maintain the reference voltage. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：即使使构成启动电路的晶体管导通所需的电压Vt相对较高，也可提供保持稳定工作的基准电压发生电路。 解决方案：在参考电压产生电路中，节点N5的电位在通电时同时输入到包括在启动电路30a中的NMOS晶体管33的栅极。 节点N5的电位通过由电阻器43产生的电位差而比输出节点N1高。因此，当在输出节点的电位之前将电阻器43的值设定为超过NMOS晶体管33的Vt时， 即使构成启动电路的晶体管33的Vt相对较高，基准电压产生电路也不会输出超过基准电压的电压，并能迅速启动并稳定地保持基准电压。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003338060A

公开(公告)日：2003-11-28

申请号：JP2002146601

申请日：2002-05-21

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  NORO MASAO

IPC: G11B7/09

Abstract: PROBLEM TO BE SOLVED: To provide a tracking servo circuit, in which the comparative accuracy of laser beams for the follow-up detection is improved and the tracking servo for reading data is performed at a high speed by effectively removing the component of a superimposing offset voltage VOFF from a detected signal OUT.
SOLUTION: This servo circuit for an optical pickup, which makes the laser beams exactly converge on a pit of the optical disk, has a feature that a VCA.10 for amplifying a reflected signal IN based on the reflection of the laser beams in accordance with the voltage of a trigger signal FB, a VCA.50 for operating the amplification based on the trigger signal FB while being constituted similarly to the VCA.10, and a differential amplifier 54 for outputting the voltage of the difference between an amplified voltage V outputted by the VCA.10 and an amplified voltage VOFFD' outputted by the VCA.50, as a detection signal OUT of the laser beams, are furnished therein.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种跟踪伺服电路，其中提高用于跟踪检测的激光束的比较精度，并且通过有效地去除部件的分量来高速执行用于读取数据的跟踪伺服 来自检测信号OUT的叠加偏移电压VOFF。 解决方案：使激光束精确地会聚在光盘的凹坑上的用于光学拾取器的该伺服电路具有以下特征：用于根据激光束的反射放大反射信号IN的VCA.10 根据触发信号FB的电压，基于触发信号FB进行放大的VCA.50类似于VCA.10构成的VCA.50以及用于输出放大后的差分电压的差分放大器54 由VCA.10输出的电压V和由VCA.50输出的放大电压VOFFD'作为激光束的检测信号OUT。 版权所有（C）2004，JPO

公开(公告)号：JP2000040359A

公开(公告)日：2000-02-08

申请号：JP20404898

申请日：1998-07-17

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C11/405

Abstract: PROBLEM TO BE SOLVED: To efficiently execute the reading and writing (refreshing) of data by eliminating a special period for precharging. SOLUTION: This circuit is provided with memory cells which store charge corresponding to levels of bit lines Bit by instructions of write word lines WWrd at the time of write-in and on the other hand which transit levels of the bit lines Bit corresponding to the stored charge by instructions of read word lines RWrd at the time of readout, transistors 11 connecting the bit lines Bit to a power source voltage Vdd at the time of readout, an inverter 12 reading out data written in the memory cells by whether the levels of the bit lines Bit are transited from pull-up levels or not at the time of readout and an inverter 15 which selects read out data or data which are to be newly written by selectors 14 and transits the levels of the bit lines Bit to the levels corresponding to the data.