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    WAFER SCALE DIE HANDLING
    14.
    发明申请
    WAFER SCALE DIE HANDLING 审中-公开

    公开(公告)号：WO2005091868A3

    公开(公告)日：2009-03-26

    申请号：PCT/US2005005641

    申请日：2005-02-23

    Applicant: ZIPTRONIX INC ,  ENQUIST PAUL M ,  FOUNTAIN GAIUS G JR ,  PETTEWAY CARL T

    Inventor： ENQUIST PAUL M ,  FOUNTAIN GAIUS G JR ,  PETTEWAY CARL T

    IPC: H01L23/495

    CPC classification number: H01L21/67333 ,  H01L2924/0002 ,  Y10S414/135 ,  Y10S414/14 ,  Y10S414/141 ,  H01L2924/00

    Abstract: A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.

    Abstract translation: 一种华夫饼包装置，包括在所述构件的表面中具有凹部以容纳来自至少一个半导体晶片的模具的构件。 该元件与半导体晶片处理设备和/或半导体晶片处理兼容。 优选地，构件容纳来自半导体晶片的至少大部分管芯。 此外，提供了一种半导体器件组装方法，其从单个华夫饼包装置中去除裸片，将来自单个华夫饼包装置的管芯放置在半导体封装上，以从放置的管芯组装集成电路所需的所有管芯部件，并将 放置在半导体封装中以形成集成电路。 提供了另一种半导体器件组装方法，其从至少一个华夫饼包装置去除管芯，将来自至少一个华夫饼包装置的管芯放置在半导体封装上，以从集成电路所需的放置的管芯器件组件中组装，并将 放置在半导体封装中以形成集成电路。

    3D IC METHOD AND DEVICE
    16.
    发明专利
    3D IC METHOD AND DEVICE 未知

    公开(公告)号：CA2618191A1

    公开(公告)日：2007-02-22

    申请号：CA2618191

    申请日：2006-08-07

    Applicant: ZIPTRONIX INC

    Inventor： FOUNTAIN GAIUS GILLMAN JR ,  ENQUIST PAUL M ,  TONG QIN-YI

    IPC: H01L21/4763

    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrical ly interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnecte d first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structu re to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose thevia, or filled via after bonding.

    WAFER SCALE DIE HANDLING
    17.
    发明专利
    WAFER SCALE DIE HANDLING 未知

    公开(公告)号：CA2558507A1

    公开(公告)日：2005-10-06

    申请号：CA2558507

    申请日：2005-02-23

    Applicant: ZIPTRONIX INC

    Inventor： FOUNTAIN GAIUS G JR ,  PETTEWAY CARL T ,  ENQUIST PAUL M

    IPC: H01L21/67 ,  H01L23/495

    Abstract: A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.

    ROOM TEMPERATURE METAL DIRECT BONDING
    18.
    发明专利
    ROOM TEMPERATURE METAL DIRECT BONDING 未知

    公开(公告)号：CA2515375A1

    公开(公告)日：2004-08-26

    申请号：CA2515375

    申请日：2004-02-06

    Applicant: ZIPTRONIX INC

    Inventor： TONG QIN-YI ,  ENQUIST PAUL M ,  ROSE ANTHONY SCOT

    IPC: H01L21/60 ,  H01L21/98 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

    Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

    THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE
    19.
    发明专利
    THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE 未知

    公开(公告)号：CA2404270A1

    公开(公告)日：2001-09-27

    申请号：CA2404270

    申请日：2001-03-22

    Applicant: ZIPTRONIX INC

    Inventor： ENQUIST PAUL M

    IPC: H01L31/04 ,  H01L21/02 ,  H01L21/768 ,  H01L27/00 ,  H01L21/44 ,  H01L21/98 ,  H01L21/48 ,  H01L21/50

    Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

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