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公开(公告)号：US12299214B2
公开(公告)日：2025-05-13
申请号：US18447147
申请日：2023-08-09
Applicant: STMicroelectronics International N.V.
Inventor： Stefano Paolo Rivolta , Federico Rizzardini , Lorenzo Bracco
IPC: G06F3/01 , G06F3/0346
Abstract: The present disclosure is directed to lift-up gesture detection for electronic devices. An initial lift-up gesture is detected in response to an orientation change and a lift-up motion of the device being detected. The initial lift-up gesture is validated as a true lift-up gesture in a case where a shaking motion of the device is not being detected when the initial lift-up gesture is detected. If a shaking motion of the device is detected when the initial lift-up gesture is detected, the initial lift-up gesture is rejected.
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公开(公告)号：US20250150811A1
公开(公告)日：2025-05-08
申请号：US18935075
申请日：2024-11-01
Applicant: STMicroelectronics International N.V.
Inventor： Julien SAADE
Abstract: At least one transmission of scrambled data with a pseudo-random sequence generated by a scrambling polynomial and an initialization value is performed between a transmitter and a receiver. Prior to the transmission, transmitter and the receiver engage in a secret negotiation phase to specifically determine the scrambling polynomial and the initialization value for the at least one transmission.
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公开(公告)号：US20250149993A1
公开(公告)日：2025-05-08
申请号：US18386949
申请日：2023-11-03
Applicant: STMicroelectronics International N.V.
Inventor： Claudio Adragna
Abstract: According to an embodiment, a converter includes a bootstrap capacitor, a high-side switch, a low-side switch, an auxiliary switch, and a controller. The bootstrap capacitor has a first terminal coupled to a floating ground node. The high-side switch has a source terminal coupled to the bootstrap capacitor through the floating ground node. The auxiliary switch has a drain terminal coupled to the bootstrap capacitor through the floating ground node. The controller provides a first control signal to a control terminal of the high-side switch, provides a second control signal to a control terminal of the low-side switch, and provides a third control signal to a control terminal of the auxiliary switch. The third control signal is based on a condition associated with the converter after the first control signal and the second control signal deactivate the high-side switch and the low-side switch respectively.
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公开(公告)号：US12294358B2
公开(公告)日：2025-05-06
申请号：US18409083
申请日：2024-01-10
Applicant: STMicroelectronics International N.V.
Inventor： Riccardo Condorelli , Antonino Mondello , Michele Alessandro Carrano , Daniele Mangano , Fabien Laplace , Luc Garcia , Michel Cuenca
Abstract: A resettable digital stage operates when a supply voltage is higher than a threshold. A non-volatile memory stores a digital code read by a reading stage. A main power-on reset circuit generates a main reset signal controlling reset of the reading stage. A resettable volatile memory coupled to the reading stage stores a default value when reset. An auxiliary power-on reset circuit generates an auxiliary reset signal controlling reset of the volatile memory. Upon deactivation of the reset, the reading stage loads the digital code into the volatile memory. The main power-on reset circuit functions in a non-trimmed configuration response to the stored default value and in a trimmed configuration responsive to the stored digital code. The main power-on reset circuit has first and second operative thresholds which respectively fall within a first and second non-trimmed voltage range or within a first and second trimmed voltage range.
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公开(公告)号：US12293981B2
公开(公告)日：2025-05-06
申请号：US17733589
申请日：2022-04-29
Inventor： Stephane Monfray , Siddhartha Dhar , Alain Fleury
Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.
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Patent Agency Ranking
公开(公告)号：US12292780B2
公开(公告)日：2025-05-06
申请号：US18338950
申请日：2023-06-21
Inventor： Nitin Chawla , Anuj Grover , Giuseppe Desoli , Kedar Janardan Dhori , Thomas Boesch , Promod Kumar
IPC: G06F1/3287 , G05F3/24 , G06F1/3234 , G06F15/78 , G11C11/413
Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
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公开(公告)号：US20250142865A1
公开(公告)日：2025-05-01
申请号：US18494401
申请日：2023-10-25
Applicant: STMicroelectronics International N.V.
Inventor： Aurore CONSTANT , Tariq WAKRIM , Ferdinando IUCOLANO
IPC: H01L29/778 , H01L21/265 , H01L21/266 , H01L29/20 , H01L29/40 , H01L29/423 , H01L29/66
Abstract: A process for forming a high electron mobility transistor (HEMT) includes forming a semiconductor heterostructure including a channel layer of the HEMT, forming a gate layer of GaN on the channel layer, and patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. The process includes forming an isolation mask covering an active region of the semiconductor heterostructure and the gate arc and performing an ion bombardment process on an inactive region of the semiconductor heterostructure exposed by the isolation mask.
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公开(公告)号：US20250138157A1
公开(公告)日：2025-05-01
申请号：US18915289
申请日：2024-10-14
Applicant: STMicroelectronics International N.V.
Inventor： Tat Ming TEO , Yandong MAO , Andrew John PRICE , William HALLIDAY
Abstract: The present disclosure provides an optical sensor module. An example optical sensor module includes a light-emitting device; a light-receiving sensor; and a module cap adapted to at least partially cover the light-emitting device and the light-receiving sensor, the module cap being a molded cap, the molded cap being formed of a molding material comprising electrically conductive particles dispersed therein for providing electromagnetic interference shielding.
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公开(公告)号：US20250138155A1
公开(公告)日：2025-05-01
申请号：US18915164
申请日：2024-10-14
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Yandong MAO , Tat Ming TEO , Fraser WILLIAMS
Abstract: The present disclosure provides an optical sensor module. An example optical sensor module comprises: a substrate comprising first conductive pads; a module cap assembled on the substrate; a connecting flex incorporated in the module cap, the connecting flex being adapted to electrically couple at least one of the first conductive pads to at least one component mounted on and/or inside the module cap; and the connecting flex comprising at least one metal layer covered by, or encapsulated in, at least one dielectric layer.
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公开(公告)号：US20250132673A1
公开(公告)日：2025-04-24
申请号：US18489410
申请日：2023-10-18
Applicant: STMicroelectronics International N.V.
Inventor： Niccolò Brambilla , Valeria Bottarel , Sandro Rossi , Alessandro Saccà
Abstract: A DC/DC converter including a low side and a high side is disclosed. The converter includes a first switching device being part of the low side, a low side current generator configured to generate a low side current flowing in the first switching device, a second switching device, a compensation resistor coupled in series to the second switching device, a valley current reference current generator configured to generate a valley current threshold current (Ivalclth) flowing in the second switching device and in the compensation resistor for obtaining a first voltage value, and a comparator configured to compare the first voltage value and a reference voltage for generating an error signal as a function of the comparison, the error signal controlling a conductivity of the first switching device of the low side.
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