公开(公告)号：US20240171145A1

公开(公告)日：2024-05-23

申请号：US18418147

申请日：2024-01-19

Applicant: pSemi Corporation

Inventor： Jing Li ,  Emre Ayranci ,  Miles Sanner

IPC: H03G3/30 ,  H03F1/22 ,  H03F1/32 ,  H03F3/193 ,  H03F3/21 ,  H03F3/72 ,  H03G1/00 ,  H03G3/00

CPC classification number: H03G3/3036 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/211 ,  H03F3/72 ,  H03G1/0023 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/001 ,  H03F2200/156 ,  H03F2200/159 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/61 ,  H03F2203/7239 ,  H03G3/3052 ,  H03G2201/504

Abstract: A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.

公开(公告)号：US20190020322A1

公开(公告)日：2019-01-17

申请号：US16046962

申请日：2018-07-26

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03G3/30 ,  H03F3/193 ,  H03F1/32

CPC classification number: H03G3/3036 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/156 ,  H03F2200/159 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/61 ,  H03F2203/7239 ,  H03G1/0023 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3052 ,  H03G2201/504

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

公开(公告)号：US10038418B1

公开(公告)日：2018-07-31

申请号：US15479173

申请日：2017-04-04

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03G3/30 ,  H03F1/32 ,  H03F3/193

CPC classification number: H03G3/3036 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/156 ,  H03F2200/159 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/61 ,  H03F2203/7239 ,  H03G1/0023 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3052 ,  H03G2201/504

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

公开(公告)号：US20050258896A1

公开(公告)日：2005-11-24

申请号：US11096854

申请日：2005-04-01

Applicant: Thomas Bardsley ,  Matthew Cordrey-Gale ,  James Mason ,  Philip Murfet ,  Gareth Nicholls

Inventor： Thomas Bardsley ,  Matthew Cordrey-Gale ,  James Mason ,  Philip Murfet ,  Gareth Nicholls

IPC: H03F1/02 ,  H03F1/14 ,  H03F3/21 ,  H03F3/45 ,  H03F3/68 ,  H03F3/72 ,  H03G1/00 ,  H03G3/00 ,  H03G3/20

CPC classification number: H03F3/45475 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/72 ,  H03F2203/45138 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/001 ,  H03G2201/103 ,  H03G2201/504

Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage (202) enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage (201) can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal (203).

Abstract translation: 提供了改变放大器和放大器阵列的增益的方法。 放大器阵列包括与具有增益控制装置的每个放大器级并联连接的两个或更多个放大器级（201,202）。 为每个放大器级提供输入信号装置（203,204），放大器级的输入信号具有不同的幅度。 提供了用于启用和禁用放大器级（216）的装置，用于对使能的放大器级的输出进行求和以获得输出信号（212）的装置。 放大器阵列的增益具有从具有第一放大级（202）使能的低增益设置的范围，通过当第一放大器级的增益从最小增益增加到最大增益时增加增益设置，第二放大器级 （201）除了第一放大器级以及第二放大器级的增益从最小增益增加到最大增益之外，还可以使能另外的放大器级，直至达到放大器阵列的最大增益设置。 启用的每个放大器级具有递减衰减的输入信号，并且待使能的最终放大器级具有完整输入信号（203）。

公开(公告)号：US20240146272A1

公开(公告)日：2024-05-02

申请号：US18406064

申请日：2024-01-05

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03G3/30 ,  H03F1/22 ,  H03F1/32 ,  H03F3/193 ,  H03F3/21 ,  H03F3/72 ,  H03G1/00 ,  H03G3/00

CPC classification number: H03G3/3036 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/211 ,  H03F3/72 ,  H03G1/0023 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/001 ,  H03F2200/156 ,  H03F2200/159 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/61 ,  H03F2203/7239 ,  H03G3/3052 ,  H03G2201/504

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

公开(公告)号：US11870405B2

公开(公告)日：2024-01-09

申请号：US17503710

申请日：2021-10-18

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03F1/32 ,  H03F3/193 ,  H03F1/22 ,  H03F3/21 ,  H03G3/30 ,  H03F3/72 ,  H03G1/00 ,  H03G3/00

CPC classification number: H03G3/3036 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/211 ,  H03F3/72 ,  H03G1/0023 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/001 ,  H03F2200/156 ,  H03F2200/159 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/61 ,  H03F2203/7239 ,  H03G3/3052 ,  H03G2201/504

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

公开(公告)号：US20180131339A1

公开(公告)日：2018-05-10

申请号：US15808486

申请日：2017-11-09

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Peihua Ye ,  Patrick Marcus Naraine ,  Adrian John Bergsma ,  Peter Harris Robert Popplewell ,  Thomas Obkircher

IPC: H03G1/00 ,  H03F3/195 ,  H03F3/45

CPC classification number: H03G1/0088 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45179 ,  H03F3/45188 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45338 ,  H03F2203/45731 ,  H03F2203/7233 ,  H03F2203/7236 ,  H03F2203/7239 ,  H03G2201/103 ,  H03G2201/106 ,  H03G2201/504

Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.

公开(公告)号：US20180083579A1

公开(公告)日：2018-03-22

申请号：US15272103

申请日：2016-09-21

Applicant: Peregrine Semiconductor Corporation

Inventor： Hossein Noori ,  Chih-Chieh Cheng

IPC: H03F1/32 ,  H03F1/56 ,  H03F3/195 ,  H03G3/00 ,  H03G3/10

CPC classification number: H03F1/3205 ,  H03F1/56 ,  H03F3/195 ,  H03F3/72 ,  H03F2200/18 ,  H03F2200/21 ,  H03F2200/211 ,  H03F2200/213 ,  H03F2200/222 ,  H03F2200/225 ,  H03F2200/24 ,  H03F2200/243 ,  H03F2200/249 ,  H03F2200/27 ,  H03F2200/294 ,  H03F2200/297 ,  H03F2200/301 ,  H03F2200/306 ,  H03F2200/312 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/399 ,  H03F2200/417 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/495 ,  H03F2200/546 ,  H03F2200/72 ,  H03F2200/75 ,  H03G1/0029 ,  H03G1/0088 ,  H03G1/0094 ,  H03G3/001 ,  H03G3/008 ,  H03G3/10 ,  H03G2201/106 ,  H03G2201/307 ,  H03G2201/504

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

公开(公告)号：US07852151B2

公开(公告)日：2010-12-14

申请号：US12130453

申请日：2008-05-30

Applicant: Thomas J. Bardsley ,  Matthew R. Cordrey-Gale ,  James S. Mason ,  Philip J. Murfet ,  Gareth J. Nickolls

Inventor： Thomas J. Bardsley ,  Matthew R. Cordrey-Gale ,  James S. Mason ,  Philip J. Murfet ,  Gareth J. Nickolls

IPC: H03F1/14

CPC classification number: H03F3/45475 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/72 ,  H03F2203/45138 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/001 ,  H03G2201/103 ,  H03G2201/504

Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage (202) enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage (201) can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal (203).

Abstract translation: 提供了改变放大器和放大器阵列的增益的方法。 放大器阵列包括与具有增益控制装置的每个放大器级并联连接的两个或更多个放大器级（201,202）。 为每个放大器级提供输入信号装置（203,204），放大器级的输入信号具有不同的幅度。 提供了用于启用和禁用放大器级（216）的装置，用于对使能的放大器级的输出进行求和以获得输出信号（212）的装置。 放大器阵列的增益具有从具有第一放大级（202）使能的低增益设置的范围，通过当第一放大器级的增益从最小增益增加到最大增益时增加增益设置，第二放大器级 （201）除了第一放大器级以及第二放大器级的增益从最小增益增加到最大增益之外，还可以使能另外的放大器级，直至达到放大器阵列的最大增益设置。 启用的每个放大器级具有递减衰减的输入信号，并且待使能的最终放大器级具有完整输入信号（203）。

公开(公告)号：JPWO2003103137A1

公开(公告)日：2005-10-06

申请号：JP2004510108

申请日：2002-05-31

Applicant: 富士通株式会社

Inventor： 聡 丸山 ,  聡 丸山

IPC: H03F1/32 ,  H03F1/52 ,  H03F3/21 ,  H03G1/00 ,  H03G3/20 ,  H03G3/30 ,  H04K1/02

CPC classification number: H03F1/3241 ,  H03F1/3247 ,  H03F1/52 ,  H03F3/211 ,  H03G1/0088 ,  H03G3/3042 ,  H03G2201/103 ,  H03G2201/206 ,  H03G2201/307 ,  H03G2201/504

Abstract: 本発明は,共通に入力信号が入力され,それぞれから増幅された信号を出力する2つの増幅器と,2つの増幅器の出力信号を合成して出力する合成器とを有する増幅装置であって,過渡状態における増幅器の出力信号の歪成分を抑制する増幅装置を提供する。この増幅装置は,合成器の出力信号に基づいで歪補償成分を求め,求めた歪補償成分に基づいて増幅器の入力信号に歪補償を行う前置歪補償部と,2つの増幅器の双方の作動状態からいずれか一方の作動状態に移行する際,いずれか一方の作動状態から双方の作動状態に移行する際,いずれか一方の増幅器が除去される際,または,除去されたいずれか一方の増幅器が取り付けられる際に,利得を定常値よりも下げて前記入力信号を定常時よりも減衰させる利得制御部とを有する。