公开(公告)号：WO1991013396A1

公开(公告)日：1991-09-05

申请号：PCT/US1991001231

申请日：1991-02-25

Applicant: EASTMAN KODAK COMPANY

Inventor： EASTMAN KODAK COMPANY ,  D'LUNA, Lionel, J.

IPC: G06F05/06

CPC classification number: G06F5/10 ,  G06F5/065 ,  G11C7/12

Abstract: A digital line delay architecture is provided that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. The digital line delay architecture is self-multiplexing and therefore requires no external addressing for the multiplexing function, and is particularly suited for use as a video line delay in a single chip digital image processing device. In particular, a pointer unit (10) is employed to sequentially address a plurality of word storage locations provided in a storage unit (12). The pointer unit (10) includes a number of shift-registers (18) that sequentially shift a logic '1' along the length of the pointer unit to accomplish the addressing.

公开(公告)号：WO1996021897A1

公开(公告)日：1996-07-18

申请号：PCT/SE1996000010

申请日：1996-01-10

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) ,  ARVIDSSON, Carl-Erik ,  THISELL, Carl-Gustaf

Inventor： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

IPC: G06F05/06

CPC classification number: G06F5/06 ,  H03M9/00 ,  H04J3/062

Abstract: A data transmission system, in which data streams shall be transmitted with great speed between a sending clock domain and a receiving clock domain, which operate with mutually different clock speeds, includes two system part circuits (202, 206). One (202) of these system part circuits is designed to receive from the first clock domain a data stream (d1) with the clock speed of the first clock domain and, controlled by this clock speed (c11), serial/parallel convert the data stream to parallel data streams each with a clock speed being a certain fraction of the clock speed of the first clock domain. The other system part circuit (206) is designed to receive the parallel data streams (du, d1) and controlled by the clock speed (c12) of the other clock domain parallel/serial converting them to an output data stream (d2), which with the clock speed of the second clock domain is sent to the second clock domain.

Abstract translation: 一种数据传输系统，其中数据流将以相互不同的时钟速度工作的发送时钟域和接收时钟域之间以高速度传输，包括两个系统部分电路（202,206）。 这些系统部分电路中的一个（202）被设计为从第一时钟域接收具有第一时钟域的时钟速度的数据流（d1），并且由该时钟速度（c11）控制，串行/并行转换数据 流到并行数据流，每个数据流的时钟速度是第一时钟域的时钟速度的一定比例。 另一个系统部分电路（206）被设计为接收并行数据流（du，d1）并由并行/串行的另一个时钟域的时钟速度（c12）控制，将它们转换成输出数据流（d2），其中 第二个时钟域的时钟速度被发送到第二个时钟域。

公开(公告)号：WO1996007132A1

公开(公告)日：1996-03-07

申请号：PCT/US1995010508

申请日：1995-08-18

Applicant: 3COM CORPORATION

Inventor： 3COM CORPORATION ,  JOHNSON, Howard, W. ,  PATEL, Sandeep ,  RIVERS, J., R. ,  SHERER, William, P.

IPC: G06F05/06

CPC classification number: G06F13/387 ,  H04L12/44 ,  H04L25/14

Abstract: Binary data is transmitted to a network physical layer from a media access controller (10) as a series of multibit nibbles and is encoded into a multi-level data stream (178) and split among a number of transmission channels (12). The multi-level signal is then translated at a receiver back into a binary data stream. In a specific embodiment, the symbol transmission frequency on each of the transmission channels (12) is at the same frequency as the nibbles transfer rate between the media access controller (10) and the physical layer.

Abstract translation: 将二进制数据作为一系列多位半字节从媒体访问控制器（10）发送到网络物理层，并将其编码为多级数据流（178）并在多个传输通道（12）之间分配。 然后，多电平信号在接收机处被转换成二进制数据流。 在具体实施例中，每个传输信道（12）上的符号传输频率与介质访问控制器（10）和物理层之间的半字节传输速率相同。

公开(公告)号：WO1996000418A1

公开(公告)日：1996-01-04

申请号：PCT/US1995008188

申请日：1995-06-27

Applicant: LORAL FAIRCHILD CORP.

Inventor： LORAL FAIRCHILD CORP. ,  WAGGENER, William, N., Jr. ,  BRAY, Thomas, Albert

IPC: G06F05/06

CPC classification number: G06F5/065 ,  G06F2205/064

Abstract: A system and method for storing data in a linked list memory architecture maintains several key list parameters. When data to be stored is received, a memory manager determines the list in which the data belongs and retrieves several of the parameters. The parameters retrieved indicate the address of the current location at which the received data is to be stored and the address of the next location that is to be linked to the current list. The memory manager writes the data to the current location pointed to by the first address and writes the second address into a pointer field in that current location. Because the address of the next location in the list is determined before data is written to the current location, this next address can be written in the same cycle in which the data is written.

Abstract translation: 用于在链表列表存储器架构中存储数据的系统和方法维护几个关键列表参数。 当接收要存储的数据时，存储器管理器确定数据所属的列表并检索几个参数。 检索到的参数指示要存储接收到的数据的当前位置的地址和要链接到当前列表的下一个位置的地址。 存储器管理器将数据写入由第一地址指向的当前位置，并将第二个地址写入当前位置的指针字段。 因为在将数据写入当前位置之前确定列表中下一个位置的地址，所以下一个地址可以写入数据写入的相同周期。

公开(公告)号：WO1990012360A1

公开(公告)日：1990-10-18

申请号：PCT/FR1990000230

申请日：1990-04-03

Applicant: LABORATOIRE EUROPEEN DE RECHERCHES ELECTRONIQUES ... ,  GUILLON, Jean-Claude

Inventor： LABORATOIRE EUROPEEN DE RECHERCHES ELECTRONIQUES ...

IPC: G06F05/06

CPC classification number: G06F7/78 ,  G06F5/06 ,  H04N7/1696

Abstract: The invention relates mainly to a device and a process for writing in a stack-type memory device. The invention concerns the use of stacks (1) of the first in, first out (FIFO) type to unscramble television images. In order to write into such a stack (1) from a desired address, irrelevant information is first written to increment the internal counter of the stack to which there is no access. Relevant information is then written from the desired counter reading. It is possible to rewrite relevant information over the irrelevant data, for instance at the start of the stack. This invention is applicable in particular to special memories for uses not designed by the manufacturer. It is more especially applicable to the use of stacks of the first in, first out type to unscramble television images.

公开(公告)号：WO1996041256A1

公开(公告)日：1996-12-19

申请号：PCT/US1996007373

申请日：1996-05-21

Applicant: S MOS SYSTEMS, INC.

Inventor： S MOS SYSTEMS, INC. ,  CHEE, Lawrence ,  TUCKER, David

IPC: G06F05/06

CPC classification number: G06F5/06

Abstract: The present invention is directed to a display FIFO module for use in DRAM interface that includes a DRAM controller sequencer which prioritizes requests for DRAM access received from various modules, such as a CPU, a blit engine module, and a half frame buffer logic module, etc. The display FIFO module is connected between the DRAM controller sequencer and a display pipeline which is connected to a display device. The display FIFO module issues low and high priority requests for DRAM access to the DRAM controller sequencer for loading the FIFO with display data to be transferred to the display device. The low priority request is issued at the earliest time when the display FIFO is capable of accepting new data without overwriting unread data. This is determined by comparing the FIFO data level against a predetermined low threshold value. the low priority request is issued when the FIFO data level falls below or is equal to the low threshold value. A high priority request is issued when the FIFO must receive new data or FIFO underrun will occur. This is determined by comparing the FIFO data level against a predetermined high threshold value. The high priority request is issued when the FIFO data level falls below or is equal to the high threshold value. After a predetermined number of addresses have been latched by the DRAM controller sequencer to the DRAM for transferring data to the FIFO because of either the low or high priority request, or both, the display FIFO module reevaluates the FIFO data level to determine whether the FIFO data level is still below or is equal to either the low or high threshold value. If the FIFO data level is still below or equal to the low threshold value, the low priority request remains active; otherwise, the low priority request will be removed by the display FIFO module. Similarly, if the FIFO data level is still below or equal to the high threshold value, the high priority request remains active; otherwise, the high priority request will be removed by the display FIFO module. The low and high priority requests are issued independently of each other.

Abstract translation: 本发明涉及一种在DRAM接口中使用的显示FIFO模块，其包括DRAM控制器定序器，其对来自诸如CPU，blit引擎模块和半帧缓冲器逻辑模块的各种模块接收的DRAM访问的优先级排序， 显示FIFO模块连接在DRAM控制器定序器和连接到显示装置的显示管线之间。 显示FIFO模块向DRAM控制器定序器发出对DRAM访问的低优先级和高优先级请求，以将要传送到显示设备的显示数据加载到FIFO。 低优先级请求是在显示FIFO能够接受新数据而不覆盖未读取数据的最早时间发出的。 这通过将FIFO数据电平与预定的低阈值进行比较来确定。 当FIFO数据电平低于或等于低阈值时，发出低优先级请求。 当FIFO必须接收到新数据或FIFO发生欠载时，才会发出高优先级请求。 这通过将FIFO数据电平与预定的高阈值进行比较来确定。 当FIFO数据电平低于或等于高阈值时，发出高优先级请求。 在由DRAM控制器定序器将预定数量的地址锁存到用于由低优先级或高优先级请求或两者都传送到FIFO的DRAM之后，显示FIFO模块重新评估FIFO数据电平以确定FIFO 数据电平仍然低于或等于低或高阈值。 如果FIFO数据电平仍低于或等于低阈值，则低优先级请求保持有效; 否则，显示FIFO模块将删除低优先级请求。 类似地，如果FIFO数据电平仍然低于或等于高阈值，则高优先级请求保持有效; 否则，高优先级请求将被显示FIFO模块删除。 低优先级和高优先级请求彼此独立地发布。

公开(公告)号：WO1996038778A1

公开(公告)日：1996-12-05

申请号：PCT/EP1996002336

申请日：1996-05-30

Applicant: 3COM IRELAND ,  O'NEILL, Eugene ,  O'CONNELL, Anne

Inventor： 3COM IRELAND

IPC: G06F05/06

CPC classification number: G06F5/065

Abstract: A large FIFO memory device has its total available memory capacity partitioned into memory sections. The partitions are in the form of programmable delimiters in order to determine flexibly the size of the memory sections.

Abstract translation: 一个大的FIFO存储器设备的总可用内存容量分为存储器部分。 这些分区是可编程分隔符的形式，以便灵活地确定存储器部分的大小。

公开(公告)号：WO1996029644A1

公开(公告)日：1996-09-26

申请号：PCT/SE1996000332

申请日：1996-03-15

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (publ) ,  HINTUKAINEN, Kari, Anders

Inventor： TELEFONAKTIEBOLAGET LM ERICSSON (publ)

IPC: G06F05/06

CPC classification number: G06F5/065 ,  G06F2205/064

Abstract: The invention relates to an arrangement and a method respectively for handling or getting access to a digital buffer in a digital buffer memory (JBUM) wherein to each digital buffer a set of pointers is arranged in a reference memory (REFM). The arrangement comprises a register arrangement (JBSR, JBER) defining the position of a digital buffer in the digital buffer memory (JBUM), an offset value, an address calculation arrangement and an operating address register (JBAR). For each of the pointers in a set relating to a digital buffer, a separate pointer register (JBSR, JBER, JBIR, JBOR) is provided and address data is input and stored substantially at the same time in each pointer register corresponding to a set of pointers. The subsequent address for reading/writting in the digital buffer memory (JBUM) is calculated and stored in at least the operating address register (JBAR).

Abstract translation: 本发明涉及一种用于处理或访问数字缓冲存储器（JBUM）中的数字缓冲器的装置和方法，其中对于每个数字缓冲器，一组指针被布置在参考存储器（REFM）中。 该装置包括定义数字缓冲存储器（JBUM）中的数字缓冲器的位置的寄存器装置（JBSR，JBER），偏移值，地址计算装置和操作地址寄存器（JBAR）。 对于与数字缓冲器相关的集合中的每个指针，提供单独的指针寄存器（JBSR，JBER，JBIR，JBOR），并且地址数据基本上在相应于一组 指针。 至少在操作地址寄存器（JBAR）中计算并存储数字缓冲存储器（JBUM）中读/写的后续地址。

公开(公告)号：WO1993021575A1

公开(公告)日：1993-10-28

申请号：PCT/JP1993000464

申请日：1993-04-12

Applicant: SEIKO EPSON CORPORATION

Inventor： SEIKO EPSON CORPORATION ,  LIN, Chong, Ming ,  WERNER, Raymond, J.

IPC: G06F05/06

CPC classification number: G06F5/16 ,  G06F3/0626 ,  G06F3/0656 ,  G06F3/0679 ,  G06F5/06 ,  G06F2003/0691 ,  G11C7/1036 ,  G11C19/28

Abstract: A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage can be fabricated using much less chip area per bit than the first and third memory stages. Significant area reduction is achieved because the second memory stage eliminates addressing overhead associated with conventional high-density memory schemes, and low voltage power supplies permit relaxation of latch-up prevention layout rules.

Abstract translation: 缓冲存储器架构，方法和芯片平面图允许显微减少微电子器件中任何给定尺寸的缓冲存储器所需的物理区域。 不需要对缓冲数据进行随机访问的缓冲应用程序使用具有提供的电压小于提供给其相应n阱的电压的正电压的p沟道器件的CMOS动态串行存储器。 在特定实施例中，以级联方式使用三个存储器级。 第一和第三存储器级以并行方式存储数据，而第二存储器级以串行方式存储数据。 可以使用比第一和第三存储器级更少的每位芯片面积制造第二存储器级。 实现了显着的面积减小，因为第二存储器级消除了与常规高密度存储器方案相关联的寻址开销，并且低压电源允许松开防闩锁布局规则。

公开(公告)号：WO1998012623A1

公开(公告)日：1998-03-26

申请号：PCT/US1997015792

申请日：1997-09-08

Applicant: HONEYWELL INC.

Inventor： HONEYWELL INC. ,  GERHART, Paul, B.

IPC: G06F05/06

CPC classification number: G06F5/10

Abstract: A single port First-In-First-Out (FIFO) data storage device that include an over-write protection feature and diagnostic capabilities. The FIFO contemplated by the invention is fabricated using a field programmable gate array; yet is as robust (feature rib) and can be used as safely as more elaborate, hardware-consuming FIFO devices, such as a traditional "dual port" FIFO. More particularly, a FIFO single port storage device (and corresponding methods for operating same) is set forth which includes (a) a write protection feature to ensure that the FIFO contents are not disturbed once the FIFO becomes full; (b) a first diagnostic feature to provide host software with an indication that the protection feature is in-force; and (c) a second diagnostic feature which provides host software with an indication that it (the software) may have errantly attempted to disturb a full FIFO before securely and completely emptying the FIFO's contents.

Abstract translation: 单端口先进先出（FIFO）数据存储设备，包括写写保护功能和诊断功能。 本发明设想的FIFO使用现场可编程门阵列制造; 而且是鲁棒的（特征肋），并且可以像更传统的“双端口”FIFO那样更精细，耗费硬件的FIFO设备安全地使用。 更具体地，阐述了FIFO单端口存储设备（以及用于操作它的相应方法），其包括（a）写保护特征，以确保一旦FIFO满满，FIFO内容不被干扰; （b）第一诊断特征，为主机软件提供保护特征有效的指示; 和（c）第二诊断特征，其向主机软件提供其指示（软件）在安全地且完全清空FIFO的内容之前可能已经错误地尝试干扰完整的FIFO。