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    Voice buffer management
    1.
    发明公开
    Voice buffer management 失效
    语音缓存管理

    公开(公告)号：EP0218073A3

    公开(公告)日：1988-02-24

    申请号：EP86111772

    申请日：1986-08-26

    Applicant: International Business Machines Corporation

    Inventor： Pham, Xuan Nghi ,  Wilson, John Hayden

    IPC: G06F03/16 ,  G06F05/06

    CPC classification number: G06F5/10 ,  G06F3/16

    Abstract: In a signal processing environment, voice messages are stored into and read out of a buffer in real time. Since voice messages are being stored and read from the buffer, different sizes and rates of information are being stored therein. Small packets of digitized voice are input to the buffer at a very high rate, while larger packets of data are output from the buffer at a lower rate and can be stored into permanent memory. The buffering of this digitized voice data occurs in real time using a ringed buffer. The transfer of data into and out of the buffer is under the control of a software application running on a host processing system. The producer of the digitized voice data is a signal processing system which converts an input analog voice signal into a compressed digitized signal. The consumer of the buffered digitized voice data is a software application program which removes blocks of multiple data records from the buffer for program execution.

    Data recording system for registering given quantities of goods, particularly milk deliveries
    4.
    发明公开
    Data recording system for registering given quantities of goods, particularly milk deliveries 失效
    数据记录系统，用于注册商品的特殊量，特别是奶制品

    公开(公告)号：EP0055806A3

    公开(公告)日：1983-07-20

    申请号：EP81108823

    申请日：1981-10-23

    Applicant: Schönhuber, Max Josef, Dr.-Ing.

    Inventor： Schönhuber, Max Josef, Dr.-Ing.

    IPC: G06K17/00 ,  G06F05/06

    CPC classification number: G06K17/00 ,  G06K2017/0058 ,  G06Q10/087 ,  G06Q40/12 ,  G07C5/085

    Abstract: Es wird ein Datenregistrierungssystem zur Erfassung der Daten von bestimmten Gutmengen, insbesondere von Mitchlieferungen vorgeschlagen, die mittels eines Sammel transportfahrzeugs eingesammelt werden sollen. Die in einem Registriergerät des Sammeltransportfahrzeugs einge gebenen Daten können auf mindestens zwei ortsfest aufge stellte Datenverarbeitungsgeräte übertragen werden, wobei eine Konvertiereinrichtung am Ort der Sammelstelle ein gangsseitig die Daten der Speichermittel des Registriergerä tes vom Sammeltransportfahrzeug her aufnimmt und aus gangsseitig aus der Konvertiereinrichtung körperlich ent nehmbare Datenträger darbietet oder aber einen Teil der Daten auf einem körperlich entnehmbaren Datenträger dar bietet, während ein anderer Teil der Daten ohne den Umweg über einen entnehmbaren Datenträger unmittelbar zu einem der Datenverarbeitungsgeräte übertragen wird.

    Buffer system with detection of read or write circuits' failures
    5.
    发明公开
    Buffer system with detection of read or write circuits' failures 失效
    检测读或写电路故障的缓冲系统

    公开(公告)号：EP0185924A3

    公开(公告)日：1988-08-03

    申请号：EP85114669

    申请日：1985-11-19

    Applicant: International Business Machines Corporation

    Inventor： Casper, Daniel F.

    IPC: G06F11/10 ,  G06F05/06 ,  G06F07/00

    CPC classification number: G06F7/785 ,  G06F5/10 ,  G06F11/1008 ,  G06F11/1076

    Abstract: An improved data buffer has a storage tray (14) that is addressable for read and write operations by an address of n bits that are supplied by a read address counter (16) and a write address counter (18) which each have n+1 bits. The (n+1)th bit is in effect a modulo-2 counter for passes through the array by the read and write circuits. During a write operation the (n+1)th bit (44) of the write counter (18) is stored as part of a parity bit (P) for the addressed array location. During a read operation the (n+1)th bit (51) of the read address counter (16) is entered into a parity checking function (30) on the word read (25) from the addressed location. An error is signalled if the (n+1)th bit of the read address counter does not agree with the (n + 1)th bit of the write counter at the time of the write operation. For example, an error is detected if the write circuits fail and the read circuits make a second pass through words that have not previously been read. This prevents reading the same entries on a next pass through the array (14).

    A METHOD AND ARRANGEMENT TO EFFECTIVELY RETRIEVE DATA FROM A BUFFER
    7.
    发明申请
    A METHOD AND ARRANGEMENT TO EFFECTIVELY RETRIEVE DATA FROM A BUFFER 审中-公开
    一种有效地从缓冲区中检索数据的方法和方案

    公开(公告)号：WO1998021647A1

    公开(公告)日：1998-05-22

    申请号：PCT/US1997020738

    申请日：1997-11-14

    Applicant: CIRRUS LOGIC, INC.

    Inventor： CIRRUS LOGIC, INC. ,  NOOKALA, Narasimha ,  SIVAMANI, Kameswaren ,  SPONRING, Otto

    IPC: G06F05/06

    CPC classification number: G06F5/06

    Abstract: A mechanism to effectively retrieve residual data received from a serial data source is provided. As the shift register receives serial data from the serial data source, the activities and content of the shift register is monitored. Status bits are set to reflect the activities and content. These status bits are used to determine whether the shift register contains residual data and whether such residual data should be ignored the serial data received from the serial data source is output to a destination.

    Abstract translation: 提供了一种有效检索从串行数据源接收的残留数据的机制。 当移位寄存器从串行数据源接收串行数据时，监视移位寄存器的活动和内容。 状态位被设置为反映活动和内容。 这些状态位用于确定移位寄存器是否包含残差数据，以及是否忽略这种残留数据，将从串行数据源接收的串行数据输出到目的地。

    METHOD AND APPARATUS FOR THE MANAGEMENT OF QUEUE POINTERS BY MULTIPLE PROCESSORS IN A DIGITAL COMMUNICATIONS NETWORK
    8.
    发明申请
    METHOD AND APPARATUS FOR THE MANAGEMENT OF QUEUE POINTERS BY MULTIPLE PROCESSORS IN A DIGITAL COMMUNICATIONS NETWORK 审中-公开
    在数字通信网络中由多个处理器管理队​​列的方法和装置

    公开(公告)号：WO1996031820A1

    公开(公告)日：1996-10-10

    申请号：PCT/US1996004517

    申请日：1996-04-02

    Applicant: STRATACOM, INC.

    Inventor： STRATACOM, INC. ,  KAO, Ruey

    IPC: G06F05/06

    CPC classification number: G06F5/06 ,  G06F2205/064

    Abstract: A method for managing a buffer queue that stores a data queue, wherein the data queue comprises a set of n data elements, n being at least zero. A head pointer is stored at a first location, which may be in a cache controlled by a first processor. The head pointer indicates a head buffer of the buffer queue. The first processor reads the head pointer to determine the head buffer of the buffer queue when a data element is to be removed from the data queue. The first processor reads a next pointer of the head buffer to determine whether the data queue is empty. The first processor determines that the data queue is empty when the next pointer has a first value, which indicates that the head buffer is a dummy buffer.

    Abstract translation: 一种用于管理存储数据队列的缓冲器队列的方法，其中所述数据队列包括一组n个数据元素，n至少为零。 头指针存储在第一位置，第一位置可以在由第一处理器控制的高速缓存器中。 头指针指示缓冲区队列的头缓冲区。 当数据元素要从数据队列中删除时，第一个处理器读取头指针以确定缓冲区队列的头缓冲区。 第一个处理器读取头缓冲区的下一个指针，以确定数据队列是否为空。 当下一个指针具有第一个值时，第一个处理器确定数据队列为空，这表示头缓冲区是一个虚拟缓冲区。

    FIFO MEMORY SYSTEM
    9.
    发明申请
    FIFO MEMORY SYSTEM 审中-公开
    FIFO存储器系统

    公开(公告)号：WO1997037298A1

    公开(公告)日：1997-10-09

    申请号：PCT/GB1997000952

    申请日：1997-03-26

    Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

    Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  KASYON, Jeffrey, D. ,  JANDER, Mark, J.

    IPC: G06F05/06

    CPC classification number: G06F5/06

    Abstract: The invention provides for a first-in-first-out (FIFO) memory system having a first fall-through FIFO (102; 302) having an input and an output, a pointer-based FIFO having an input and an output, wherein the input of the pointer-based FIFO (104; 304) is connected to the output of the first fall-through FIFO, and a second fall-through FIFO (106; 306) having an input and an output, wherein the input of the second fall-through FIFO (106; 306) is connected to the output of the pointer-based FIFO (104; 304), wherein data placed into the input of the first fall-through FIFO (102; 302) appears at the output of the second fall-through FIFO (106; 306) in a first-in-first-out basis.

    Abstract translation: 本发明提供了具有具有输入和输出的第一下降FIFO（102; 302）的先进先出（FIFO）存储器系统，具有输入和输出的基于指针的FIFO，其中， 基于指针的FIFO（104; 304）的输入连接到第一下降FIFO的输出端和具有输入和输出的第二下降FIFO（106; 306），其中第二 直通FIFO（106; 306）连接到基于指针的FIFO（104; 304）的输出，其中放置在第一下降FIFO（102; 302）的输入中的数据出现在 第二通过FIFO（106; 306）。

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