公开(公告)号：US10530563B2

公开(公告)日：2020-01-07

申请号：US15898816

申请日：2018-02-19

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Etienne Cesar

IPC: H04L7/033 ,  H03L7/085 ,  H03L7/099

Abstract: In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.

公开(公告)号：US20200005872A1

公开(公告)日：2020-01-02

申请号：US16432369

申请日：2019-06-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Leonardo Valencia Rissetto ,  Elise Le Roux ,  Christophe Forel

IPC: G11C16/10 ,  G11C16/04

Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.

公开(公告)号：US20190376676A1

公开(公告)日：2019-12-12

申请号：US16439308

申请日：2019-06-12

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Joseph HANNAN ,  Stuart ROBERTSON ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: F21V23/04 ,  H05B33/08 ,  F21V23/00 ,  H01L33/44 ,  H01L23/00 ,  F21K9/20

Abstract: The disclosure concerns a housing for a light source mounted on a substrate, the housing comprising: a molded body having an opening permitting the passage of a light beam generated by the light source; one or more surfaces for receiving a diffuser; and first and second conducting pins traversing the molded body, each pin abutting one of said surfaces.

公开(公告)号：US20190356390A1

公开(公告)日：2019-11-21

申请号：US16409723

申请日：2019-05-10

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Alexandre COULLOMB ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: H04B10/40 ,  H04B10/50 ,  H04B10/69 ,  H01L31/0203 ,  H01L25/04

Abstract: An optoelectronic device includes a substrate and a first optoelectronic chip flush with a surface of the substrate. The device includes a cover that covers the substrate and the first optoelectronic chip. The cover comprises a cavity above a first optical transduction region of the first optoelectronic chip. The device also includes a second optoelectronic chip having a second optical transduction region spaced apart from the first optical transduction region and the cavity continues above the second optical transduction region.

公开(公告)号：US20190355674A1

公开(公告)日：2019-11-21

申请号：US16411960

申请日：2019-05-14

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Denis FARISON ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/56 ,  H01L25/065

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

公开(公告)号：US10483181B2

公开(公告)日：2019-11-19

申请号：US16035083

申请日：2018-07-13

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Karine Saxod ,  Nicolas Mastromauro

IPC: H01L23/12 ,  H01L23/31 ,  H01L23/32 ,  H01L23/04 ,  H01L23/10

Abstract: An integrated circuit chip is mounted to a front face of a support plate. An encapsulation cap in then mounted to the support plate. The encapsulation cap includes a front wall and a peripheral wall having an end edge at least partly facing a peripheral zone of the support plate. The support plate and the encapsulation cap delimit a chamber in which the integrated circuit chip is situated. To mount the encapsulation cap, a bead of glue is inserted between the peripheral zone and the end edge of the peripheral wall of the encapsulation cap. A peripheral outer face of the encapsulation cap includes a recess extending from the end edge which locally uncovers a part of the bead of glue. A local hardening of the glue at the recess is performed as a first attachment step. Further hardening of the remainder of the glue is then performed.

公开(公告)号：US20190333859A1

公开(公告)日：2019-10-31

申请号：US16390889

申请日：2019-04-22

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Eric SAUGIER

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/768

Abstract: The disclosure concerns a semiconductor chip, which may be an interposer, having conductive through vias having a parallelepipedal shape.

公开(公告)号：US20190268043A1

公开(公告)日：2019-08-29

申请号：US16286345

申请日：2019-02-26

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gwenael Maillet ,  Jean-Louis Labyre ,  Gilles Bas

IPC: H04B5/00

Abstract: A system includes a near-field communication device configured to transmit a radio frequency control signal in a near-field regime and an interface. The interface includes a near-field communication circuit configured to receive the RF control signal. The interface further includes a pulse width modulation signal generation circuit configured to generate a pulse width modulation signal according to the radio frequency control signal. The system further includes an electrically-controllable equipment configured to be controlled by the pulse width modulation signal.

公开(公告)号：US20190267349A1

公开(公告)日：2019-08-29

申请号：US16282594

申请日：2019-02-22

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Marie-Astrid PIN ,  Karine SAXOD ,  Jean-Michel RIVIERE

IPC: H01L23/00 ,  H01L31/0203 ,  H01L33/48 ,  H01L21/78

Abstract: Individual electronic units are formed by cutting a collective assembly. A collective support plate is provided which includes electronic chips. A collective cover plate is provided which includes ribs defining recesses. The collective assembly is formed by mounting the collective cover plate to the collective support plate in a manner where the electronic chips are located in the recesses and the ribs are located between electronic chips. A bead of glue is interposed between ends of the ribs and the surface of the collective support plate. After the glue is hardened, a cutting operation is performed on the collective assembly by cutting through the ribs and the collective support plate to produce the individual electronic units.

公开(公告)号：US20190266462A1

公开(公告)日：2019-08-29

申请号：US16277698

申请日：2019-02-15

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gwenael Maillet ,  Jean-Louis Labyre ,  Gilles Bas

IPC: G06K19/07 ,  G06K7/00

Abstract: A method of reducing noise generated by pulse width modulation (PWM) signals includes generating a PWM pulse train using a first set of parameter values and modifying the PWM pulse train during a near-field communication so that the PWM pulse train is generated using a second set of parameter values. Modifying the PWM pulse train includes reducing at least one parameter value of the first set of parameter values. The method further includes resuming generation of the PWM pulse train using the first set of parameter values after the near-field communication.