公开(公告)号：EP1026826A2

公开(公告)日：2000-08-09

申请号：EP99310180.7

申请日：1999-12-17

Applicant: Stmicroelectronics, Ltd.

Inventor： Barnes, William

IPC: H03K5/24

CPC classification number: H03K5/249 ,  H03K3/356139 ,  H03K5/2481

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed.

Abstract translation: 具有用于比较第一和第二电压的比较装置的比较器电路具有用于向所述比较装置提供电流的电流源电路，所述电流源电路具有用于接收具有第一和第二状态的时钟信号的输入，由此比较装置开始比较 当时钟信号从第一状态转换到第二状态时的第一和第二电压; 以及用于确定何时所述比较装置已经完成所述第一和第二电压的比较以及用于在所述比较已经完成时关断所述电流源电路并因此断开所述比较装置的装置。

公开(公告)号：EP0953891A1

公开(公告)日：1999-11-03

申请号：EP99300599.0

申请日：1999-01-27

Applicant: Stmicroelectronics, Ltd.

Inventor： Barnes, William Bryan

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: A current mirror has an input node for receiving an input current and an output node for filing an output current. First, second and third transistors are provided with each transistor having first and second current path terminals and a control terminal. The control terminals of the first and second transistors are connected to each other. The first current path terminal of the first transistor and one of the current path terminals of the second transistor are connected to a power supply. The control terminal of the third transistor is connected to the input node. One of the first and second current path terminals of the third transistor are connected to the output node and the other of the first and second current path terminals of the third transistor are connected to the other of the first and second current path terminals of the second transistor. A resistive element is arranged between the input node and the second current path terminal of the first transistor. The control terminals of the first and second transistors are connected to a node between the resistive element and a second current path terminal of the first transistor. The resistive element is a transistor of the opposite plurality to the first, second and third transistors.

Abstract translation: 电流镜具有用于接收输入电流的输入节点和用于归档输出电流的输出节点。 首先，提供具有第一和第二电流路径端子和控制端子的每个晶体管的第二和第三晶体管。 第一和第二晶体管的控制端子彼此连接。 第一晶体管的第一电流通路端子和第二晶体管的电流通路端子之一连接到电源。 第三晶体管的控制端连接到输入节点。 第三晶体管的第一和第二电流通路端子之一连接到输出节点，第三晶体管的第一和第二电流通路端子中的另一个连接到第二晶体管的第一和第二电流通路端子中的另一个 晶体管。 电阻元件布置在第一晶体管的输入节点和第二电流路径端子之间。 第一和第二晶体管的控制端子连接到第一晶体管的电阻元件和第二电流通路端子之间的节点。 电阻元件是与第一，第二和第三晶体管相反的多个晶体管。

公开(公告)号：EP0945805A1

公开(公告)日：1999-09-29

申请号：EP99301960.3

申请日：1999-03-15

Applicant: Stmicroelectronics, Ltd.

Inventor： Jones, Andrew Michael

IPC: G06F12/08

CPC classification number: G06F12/0837 ,  G06F12/0815

Abstract: A computer system has a plurality of processors each for executing a sequence of instructions and at least one of the processors having a cache memory associated therewith. A memory provides an address space of that processor where data items are stored for use by all of the processors. A behaviour store holds in association with the address of each item a cache behaviour identifying the cacheable behaviour of the item, the cacheable behaviours including a software coherent behaviour and an automatically coherent behaviour. When a cache coherency operation is instigated by a cache coherency instruction, the operation is effected dependent on the cacheable behaviour of the specified address of the item.
A method of modifying the coherency status of a cache in this manner is also described.

Abstract translation: 计算机系统具有多个处理器，每个处理器用于执行指令序列，并且至少一个处理器具有与其相关联的高速缓冲存储器。 存储器提供该处理器的地址空间，其中存储数据项以供所有处理器使用。 行为存储与每个项目的地址相关联地存储识别项目的可缓存行为的缓存行为，可缓存行为包括软件相关行为和自动相关行为。 当缓存一致性操作由高速缓存一致性指令引发时，该操作取决于项目的指定地址的可缓存行为。 还描述了以这种方式修改高速缓存的相关性状态的方法。

公开(公告)号：EP0933926A1

公开(公告)日：1999-08-04

申请号：EP99300683.2

申请日：1999-01-29

Applicant: Stmicroelectronics, Ltd.

Inventor： MacCormack, Andrew

IPC: H04N5/00

CPC classification number: H04N21/434

Abstract: There is disclosed a controller for controlling direct memory access. Such controller is particularly applicable when applied to a transport interface in the receiver of a digital set-top-box for television systems.
Storage means stores the base and top addresses of a circular buffer in a memory to which received data is to be forwarded and stored, and a write pointer for such buffer is also stored in the storage means. Addressing circuitry generates the address to which the receive data is to be written in dependence on the stored base and top addresses and the write pointer. Output circuitry writes the data into the circular buffer at the location identified by the generated address.

Abstract translation: 公开了一种用于控制直接存储器存取的控制器。 这种控制器在应用于用于电视系统的数字机顶盒的接收机中的传输接口时特别适用。 存储装置将循环缓冲器的基地址和顶部地址存储在要被转发和存储接收数据的存储器中，并且用于这种缓冲器的写指针也存储在存储装置中。 寻址电路根据存储的基地址和顶部地址以及写入指针生成要写入接收数据的地址。 输出电路将数据写入由生成的地址标识的位置的循环缓冲区。

公开(公告)号：EP3383032A1

公开(公告)日：2018-10-03

申请号：EP17186470.5

申请日：2017-08-16

Applicant: STMicroelectronics Ltd

Inventor： ADLER, Gilad ,  SOURANI, Sason

IPC: H04N9/31

CPC classification number: H04N7/0127 ,  G02B26/0833 ,  G02B26/101 ,  G02B26/105 ,  G09G3/02 ,  G09G2310/0224 ,  H04N9/3129 ,  H04N9/3161 ,  H04N9/3164 ,  H04N9/3188

Abstract: An electronic device includes a first laser source (101a) configured to project a first laser beam (107a), and a second laser source (101b) configured to project a second laser beam (107b) in alignment with the first laser beam in a first direction but at an angle with respect to the first laser beam in a second direction. A mirror apparatus (110) is positioned so as to reflect the first and second laser beams. Control circuitry (130) is configured to control the mirror apparatus to simultaneously reflect the first and second laser beams in a first scan pattern to form an first image, the first image formed from the first scan pattern having a number of scan lines greater than two times a horizontal resonance frequency at which the mirror apparatus oscillates divided by a desired frame rate of the first image.

公开(公告)号：EP1768408A1

公开(公告)日：2007-03-28

申请号：EP05254789.0

申请日：2005-07-29

Applicant: STMicroelectronics Ltd.

Inventor： Dellow, Andrew ,  Bennett, Peter

IPC: H04N7/167 ,  H04L9/00

CPC classification number: H04N7/1675 ,  H04L9/0891 ,  H04L9/3247 ,  H04L2209/56 ,  H04L2209/601 ,  H04N21/4181 ,  H04N21/43607 ,  H04N21/4405 ,  H04N21/8166

Abstract: A method, apparatus and system for restricting the use of a data item (PBK1) stored within a circuit (3), the method comprising the steps of:
- receiving and storing the data item in the circuit (3);
- receiving a signature (201), the signature (201) being derived from data in a data item field (hash of PBK1=H(PBK1)-207) and data in one or more value fields (VCC 203, STC 205), the signature (201) being in a (RSA) coded form generated according to a predetermined algorithm (RSA):
- decoding the signature (201) and extracting information representative of the data H(PBJ1) in the data item field (207) and information representative of the values VCC & STC in the one or more value fields (203, 205);
- determining whether the information representative of the data extracted from the data item field (207) of the signature (201) corresponds to a predetermined value stored in the circuit (3) and whether the information representative of each value extracted from each value field (203,205) of the signature (201) corresponds to a corresponding further predetermined value stored in the circuit (3); and
- generating a comparison signal according to the result of the determinations;
in which use of the data item (PBK1) is restricted according to the state of the comparison signal.

Abstract translation: 对于限制使用的数据项的方法，设备和系统（PBK1）存储在电路（3）内，该方法包括以下步骤： - 接收和在电路（3）存储数据项; - 接收的签名（201），签名（201）被从数据导出的数据项字段（散列PBK1 = H（PBK1）-207），并且在一个或多个值字段中的数据（VCC 203，STC 205） 在（RSA）编码的形式是所述签名（201）生成的雅丁预定算法（RSA）： - 解码签名（201），并提取代表该数据项字段（207）中的数据H（pBJ1）的信息和 代表值VCC＆STC在所述一个或多个值的字段（203，205）的信息; - 确定性采矿是否代表从签名（201）的数据项字段（207）中提取的数据的信息对应于存储在电路中的预定值（3），以及是否代表从每个值字段提取的每个值的信息（ 签名（201）的203.205）对应于存储在电路（3）的相应的另外的预定值; 以及 - 产生一个比较信号gemäß到的确定的结果; 在其中使用的数据项（PBK1）的被限制gemäß于比较信号的状态。

公开(公告)号：EP1760619A1

公开(公告)日：2007-03-07

申请号：EP05255129.8

申请日：2005-08-19

Applicant: STMicroelectronics Ltd.

Inventor： DELLOW, Andrew ,  BENNETT, Peter

IPC: G06F21/00 ,  H04N5/00

CPC classification number: H04N21/443 ,  H04H60/23 ,  H04H60/80

Abstract: An initiator transmits a data access command to a data source or destination containing an identification of the initiator and of the data source or destination. A security filter compares the identifications with a list of those initiators defined as secure and a list of those data sources or destinations which are defined as unprivileged. The filter then blocks or allows the data access command signal according to a set of rules. In one embodiment, the most secure initiator is a security control circuit which is authorised to access all data sources or destinations. The other secure initiators are authorised to access only specified unprivileged data sources or destinations and the insecure initiators are not authorised to access any data sources or destinations. The information relating to which initiators are secure and insecure and which data sources or destinations are privileged and unprivileged is loaded during an initialisation procedure by the security control circuit in response to a configuration command transmitted by a processor. In order that the configuration command is not blocked by the security filter before the processor is authorised to access the security control circuit prior to initialisation, the configuration command is verified using a signature check.

Abstract translation: 启动器将数据访问命令发送到包含发起者和数据源或目的地的标识的数据源或目的地。 安全过滤器将标识与定义为安全性的那些启动器的列表以及定义为无特权的那些数据源或目标的列表进行比较。 然后，滤波器根据一组规则阻止或允许数据访问命令信号。 在一个实施例中，最安全的启动器是被授权访问所有数据源或目的地的安全控制电路。 其他安全启动器被授权仅访问指定的非特权数据源或目的地，而不安全启动器则无权访问任何数据源或目的地。 响应于由处理器发送的配置命令，由安全控制电路在初始化过程期间加载与哪些发起者是安全的和不安全的以及哪些数据源或目的地是特权和非特权的信息。 为了在处理器被授权在初始化之前访问安全控制电路之前配置命令不被安全过滤器阻止，使用签名检查验证配置命令。

公开(公告)号：EP0908834B1

公开(公告)日：2006-08-16

申请号：EP98307486.5

申请日：1998-09-15

Applicant: STMicroelectronics Ltd.

Inventor： Barrett, Geoff

IPC: G06F17/50

CPC classification number: G06F17/504

公开(公告)号：EP1450536A1

公开(公告)日：2004-08-25

申请号：EP03251091.9

申请日：2003-02-24

Applicant: STMicroelectronics, Ltd.

Inventor： Morris, Matt

IPC: H04L29/06 ,  H04L12/56

CPC classification number: H04L49/25 ,  H04L49/103

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination port. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract translation: 讨论数据流的路由，并且特别地将一个或多个输入流路由到一个或多个输出目的地端口。 讨论合并输入流的能力，使得几个低比特率输入分组流可以被合并到更高比特率的输出流中。 分配数据结构为每个输入流标识其要路由的每个目的地，并且分组分配数据结构保存关于分组的信息和关于分组的目的地的信息，以允许控制分组的存储器 因此。

公开(公告)号：EP1426872A2

公开(公告)日：2004-06-09

申请号：EP03027181.1

申请日：2003-11-27

Applicant: STMicroelectronics Ltd.

Inventor： Saha, Kaushik ,  Maiti, Srijib Narayan

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: This invention relates to a linear scalable method for computing a Fast Fourier Transform (FFT) or Inverse Fast Fourier transform (IFFT) in a multiprocessing system using a decimation in time approach. Linear scalability means, as the number of processors increases by a factor P (for example), the computational cycle reduces by exactly the same factor P. The invention comprises computing the first two stages of an N-point FFT/IFFT as a single radix-4 butterfly computation operation while implementing the remaining (log 2 N-2) stages as radix-2 operations, fusing the 3 main nested loops of each radix-2 butterfly stage into a single radix-2 butterfly computation loop, and distributing the computation of the butterflies in each stage such that each processor computes an equal number of complete butterfly calculations thereby eliminating data interdependency in the stage.

Abstract translation: 本发明涉及一种用于在使用时间抽取方法的多处理系统中计算快速傅里叶变换（FFT）或快速傅里叶逆变换（IFFT）的线性可伸缩方法。 线性可伸缩性意味着，随着处理器的数量增加因子P（例如），计算周期减少了完全相同的因子P.本发明包括将N点FFT / IFFT的前两个阶段计算为单个基数 -4蝴蝶计算操作，同时将剩下的（log 2 N-2）级作为基数-2操作，将每个基数-2蝶形阶段的3个主嵌套循环融合到单个2进制蝶形运算循环中，并分配计算 的每个阶段的蝴蝶，使得每个处理器计算相等数量的完整蝴蝶计算，从而消除阶段中的数据相互依赖性。