公开(公告)号：US20020031015A1

公开(公告)日：2002-03-14

申请号：US09952904

申请日：2001-09-13

Applicant: STMicroelectronics S.A.

Inventor： Bertrand Bertrand ,  David Naura ,  Sebastien Zink

IPC: G11C005/00

CPC classification number: G11C7/12 ,  G11C16/24

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2P bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2pnull2q other data in the 2pnull2q llow-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2pnullqnull1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract translation: 集成电路存储器的列寄存器，特别是在EEPROM技术中，用于将2P位的数据字写入存储器的方法，其中p是非零整数。 该方法包括以下步骤：1）擦除字的所有单元; 2）在qp高压锁存器（HV1，HV3，HV5，HV7）中加载2q数据，并在2p-2q低压锁存器（LV0，LV2，LV4，LV6）中加载2p-2q其他数据; 和3）根据存储在2q高电压锁存器中的数据来编程存储器（M0，M2，M4，M6）的2q个单元; 以及重复2p-q-1次以下步骤：4）在步骤2）中加载2q高电压锁存器中的2q其他数据的2q高电压锁存器; 和5）根据存储在2q高电压锁存器中的数据来编程存储器（M1，M3，M5，M7）的2q个其他单元。

公开(公告)号：US20020018367A1

公开(公告)日：2002-02-14

申请号：US09896817

申请日：2001-06-29

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel

IPC: G11C016/30

CPC classification number: G11C5/143 ,  G11C16/12

Abstract: An integrated circuit having as power supply voltages a low voltage reference, a logic supply voltage reference and a high voltage reference is provided. The high voltage reference is greater than the low voltage reference and the logic supply voltage reference. The integrated circuit includes an electrically programmable non-volatile memory element, and a selection and programming circuit connected thereto. A voltage control device is connected to a power supply input node of the selection and programming circuit for applying, based upon a programming control signal, the high voltage reference for programming the electrically programmable non-volatile memory element or for applying at least one logic supply voltage reference.

Abstract translation: 提供具有作为电源电压的低电压基准，逻辑电源电压基准和高电压基准的集成电路。 高电压参考值大于低电压参考电压和逻辑电源参考电压。 集成电路包括电可编程非易失性存储器元件以及与其连接的选择和编程电路。 电压控制装置连接到选择和编程电路的电源输入节点，用于基于编程控制信号将用于编程电可编程非易失性存储器元件的高电压参考值或用于施加至少一个逻辑电源 电压参考。

公开(公告)号：US20020012067A1

公开(公告)日：2002-01-31

申请号：US09852962

申请日：2001-05-10

Applicant: STMicroelectronics S.A.

Inventor： Vincent Tauzia

IPC: H04N011/00

CPC classification number: H04N5/44543 ,  H04N7/0882 ,  H04N21/4312 ,  H04N21/4888

Abstract: A teletext program includes several teletext pages, with each teletext page being broadcast in the form of a set of data packets. A method for displaying a teletext program index on a television receiver screen includes receiving a teletext page which includes the set of data packets. The set of data packets includes first and second data packets. The first data packet includes at least one label referring to another teletext page, and the second data packet is associated with the first data packet and includes a page number associated with at least one label. The method includes decoding the first and second data packets to obtain at least one label and the associated page number, and at least one label and the associated page number are stored in a buffer memory.

Abstract translation: 图文电视节目包括几个图文电视页面，每个图文电视页面以一组数据分组的形式进行广播。 一种用于在电视接收机屏幕上显示图文电视节目索引的方法包括接收包括该组数据分组的图文电视页面。 该组数据分组包括第一和第二数据分组。 第一数据分组包括至少一个引用另一图文页面的标签，并且第二数据分组与第一数据分组相关联并且包括与至少一个标签相关联的页码。 该方法包括对第一和第二数据分组进行解码以获得至少一个标签和相关联的页面编号，并且至少一个标签和相关页面编号被存储在缓冲存储器中。

公开(公告)号：US20020004918A1

公开(公告)日：2002-01-10

申请号：US09870121

申请日：2001-05-30

Applicant: STMicroelectronics S.A.

Inventor： Frederic Mathieu ,  Frederic Bard

IPC: G06F011/00

CPC classification number: G06F11/2236 ,  G01R31/31835 ,  G06F11/261

Abstract: A method is for the preparation and execution of a self-test procedure to validate the behavior of a processor model to be tested. The processor model may be a processor or an associated simulator. The method provides self-test procedures that are immediately executable by all the models of a processor and that give OK/ERROR type results that are easy to interpret.

Abstract translation: 一种方法是准备和执行自检程序，以验证要测试的处理器模型的行为。 处理器模型可以是处理器或相关联的模拟器。 该方法提供了可以由处理器的所有型号立即执行的自检程序，并给出易于解释的OK / ERROR类型结果。

公开(公告)号：US20020003586A1

公开(公告)日：2002-01-10

申请号：US09827306

申请日：2001-04-05

Applicant: STMicroelectronics S.A.

Inventor： Pierre Busson ,  Pierre-Olivier Jouffre ,  Frederic Paillardet

IPC: H04N007/20 ,  H04N005/50

CPC classification number: H03G3/3068 ,  H03G3/3089

Abstract: A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/ amplifier stage being fixed.

Abstract translation: 调谐器包括模拟块，数字块和连接在它们之间的模拟/数字转换级。 模拟模块包括连接到频率转置级上游的第一衰减器/受控增益放大器级。 在初始化阶段计算由调谐器接收的整个信号的总平均功率。 该总计算功率在数字模块中与对应于模拟模块的预定位置所需的最大功率的第一预定参考值进行比较。 调整第一衰减器/放大器级的增益以最小化总计算功率与参考值之间的偏差。 在正常工作阶段，选择所接收信号的通道之一，第一衰减器/放大器级的增益是固定的。

公开(公告)号：US20020003286A1

公开(公告)日：2002-01-10

申请号：US09930084

申请日：2001-08-15

Applicant: STMICROELECTRONICS S.A.

Inventor： Michel Marty ,  Alain Chantre ,  Jorge Regolini

IPC: H01L029/70

CPC classification number: H01L29/66242 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.

Abstract translation: 垂直双极晶体管包括SiGe异质结基底，其由沉积在围绕本征收集器的上部的侧绝缘区域延伸的氮化硅初始层上的硅层和硅锗叠层形成。 层叠层还在固有收集器的位于形成于初始氮化硅层的窗口内部的表面上延伸。

公开(公告)号：US20010054913A1

公开(公告)日：2001-12-27

申请号：US09891964

申请日：2001-06-26

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: H03K019/20

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

Abstract translation: 一种具有数字输出的电子电路，包括闩锁（1），控制组件（2），可吹塑组件（3），连接到公共点（14）的第一输入的逻辑门（4））的自动稳定组件， 在自动稳定组件（1）和可吹塑组件（3）之间，以及连接到电子电路的控制输入（20）的第二输入。 断路器（5）由逻辑门（4）的输出控制并且布置在自动稳定组件（1）和地之间，以及相关联的过程。

公开(公告)号：US20010053584A1

公开(公告)日：2001-12-20

申请号：US09817898

申请日：2001-03-26

Applicant: STMicroelectronics S.A.

Inventor： Alain Chantre ,  Didier Dutartre ,  Helene Baudry

IPC: H01L021/76

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

Abstract translation: 具有异质结基底的自对准双多晶硅型双极晶体管包括位于半导体衬底的有源区上方的半导体异质结区域和界定有源区域的隔离区域，以及掺入晶体管的本征基极区域。 位于有源区上方并与半导体异质结区的上表面接触的发射极区。 形成晶体管的非本征基极区域的多晶硅层，位于发射极区域的每一侧，并且通过分离层与半导体异质结区域分离，所述分离层包括位于发射极区域正前方的导电连接部分。 该连接部件确保外部基座和内部基座之间的电接触。

公开(公告)号：US20010050546A1

公开(公告)日：2001-12-13

申请号：US09827295

申请日：2001-04-05

Applicant: STMicroelectronics S.A.

Inventor： Nicolas Marty

IPC: G05F001/40

CPC classification number: G05F1/565 ,  G05F1/575

Abstract: A voltage regulator includes a regulation MOS transistor with low serial resistance having a first terminal connected to a voltage source and a second terminal connected to the output of the voltage regulator and an amplifier having an output driving a gate of the transistor. The gate is driven based upon a difference between a reference voltage and a feedback voltage. The regulator may also include an anti-overshoot switch with a first terminal connected to the gate of the regulation MOS transistor and a second terminal is taken to a potential for turning the regulation MOS transistor off. A switch controller closes the switch when the output voltage of the regulator is higher than a first threshold. The first threshold may be higher than the nominal value of the output voltage.

Abstract translation: 电压调节器包括具有低串联电阻的调节MOS晶体管，其具有连接到电压源的第一端子和连接到电压调节器的输出端的第二端子和具有驱动晶体管的栅极的输出的放大器。 基于参考电压和反馈电压之间的差异来驱动门。 调节器还可以包括具有连接到调节MOS晶体管的栅极的第一端子的反过冲开关，并且将第二端子置于使调节MOS晶体管截止的电位。 当调节器的输出电压高于第一阈值时，开关控制器关闭开关。 第一阈值可能高于输出电压的标称值。

公开(公告)号：US20010044922A1

公开(公告)日：2001-11-22

申请号：US09737827

申请日：2000-12-15

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: H03M013/00

CPC classification number: G06F11/1008 ,  G06F11/1032 ,  G06F2201/81 ,  H03M13/19

Abstract: A method for the correction of an erroneous bit in a string of bits includes providing, in the string of bits, for a first parity bit computed from the other bits of the string of bits at a point in time when the erroneous bit was valid. The correct value of the erroneous bit is computed by using the other bits of the string of bits comprising the parity bit. The erroneous bit is then replaced by its correct value. The method is applicable to error correction circuits in EEPROM memories.

Abstract translation: 用于校正一串比特中的错误比特的方法包括：在该比特串中，提供在该错误比特有效的时间点从该比特串的其他比特计算的第一奇偶校验位。 通过使用包括奇偶校验位的位串串的其他位来计算错误位的正确值。 错误的位被其正确的值替换。 该方法适用于EEPROM存储器中的纠错电路。