公开(公告)号：US11836426B1

公开(公告)日：2023-12-05

申请号：US17819884

申请日：2022-08-15

Applicant: Xilinx, Inc.

Inventor： Fangqing Du ,  Alexandre Isoard ,  Lin-Ya Yu ,  Hem C. Neema

IPC: G06F30/327 ,  G06F15/80

CPC classification number: G06F30/327 ,  G06F15/80

Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.

公开(公告)号：US20230376437A1

公开(公告)日：2023-11-23

申请号：US17663824

申请日：2022-05-17

Applicant: Xilinx, Inc.

Inventor： David Patrick Clarke ,  Peter McColgan ,  Juan J. Noguera Serra ,  Tim Tuan ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Javier Cabezas Rodriguez ,  Pedro Miguel Parola Duarte ,  Zachary Blaise Dickman

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.

公开(公告)号：US11824830B2

公开(公告)日：2023-11-21

申请号：US17246310

申请日：2021-04-30

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

IPC: H04L29/06 ,  H04L9/40

CPC classification number: H04L63/0227 ,  H04L63/029

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

公开(公告)号：US11824534B2

公开(公告)日：2023-11-21

申请号：US17455195

申请日：2021-11-16

Applicant: XILINX, INC.

Inventor： Nakul Narang ,  Siok Wei Lim ,  Luhui Chen ,  Yipeng Wang ,  Kee Hian Tan

IPC: H04L25/02 ,  H03K19/17736 ,  G06F13/10 ,  H03K19/17788 ,  H04J3/04

CPC classification number: H03K19/17744 ,  G06F13/102 ,  H03K19/17788 ,  H04J3/047 ,  H04L25/0272

Abstract: A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

公开(公告)号：US20230359801A1

公开(公告)日：2023-11-09

申请号：US17662037

申请日：2022-05-04

Applicant: Xilinx, Inc.

Inventor： Sreesan Venkatakrishnan ,  Nitin Deshmukh ,  Satish B. Sivaswamy

IPC: G06F30/394 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/398 ,  G06F2111/04

Abstract: Routing a circuit design includes generating a graph of the circuit design where each connected component is represented as a vertex, generating a routing solution for the circuit design by routing packet-switched nets so that the packet-switched nets of a same connected component do not overlap, and, for each routing resource that is shared by packet-switched nets of different connected components, indicating the shared routing resource on the graph by adding an edge. Cycle detection may be performed on the graph. For each cycle detected on the graph, the cycle may be broken by deleting the edge from the graph and ripping-up a portion of the routing solution corresponding to the deleted edge. The circuit design, or portion thereof, for which the routing solution was ripped up may be re-routed using an increased cost for a shared routing resource freed from the ripping-up.

公开(公告)号：US20230325333A1

公开(公告)日：2023-10-12

申请号：US18206045

申请日：2023-06-05

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  Millind MITTAL

IPC: G06F13/40 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F13/4022 ,  G06F9/30043 ,  G06F13/1663 ,  G06F13/1668 ,  G06F2209/5011 ,  G06F2213/0038

Abstract: An integrated circuit (IC) for adaptive memory expansion scheme is proposed, which comprises: a home agent comprising a first memory expansion pool and a second memory expansion pool; a first port connecting the home agent to a first memory expansion device, where the first memory expansion device comprises a first memory pool; a second port connecting the home agent to a second memory expansion device, where the second memory expansion device comprises a second memory pool; a first address table mapping the first memory expansion pool to the first memory pool based on a size of the first memory expansion pool or a size of the first memory pool; and a second address table mapping the second memory expansion pool to the second memory pool based on a size of the second memory expansion pool or a size of the second memory pool.

公开(公告)号：US20230318921A1

公开(公告)日：2023-10-05

申请号：US17657977

申请日：2022-04-05

Applicant: Xilinx, Inc.

Inventor： Chirag Ravishankar ,  Dinesh D. Gaitonde

IPC: H04L41/0893 ,  H04L49/109 ,  H04J3/02

CPC classification number: H04L41/0893 ,  H04J3/02 ,  H04L49/109

Abstract: Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

公开(公告)号：US11777489B1

公开(公告)日：2023-10-03

申请号：US17747387

申请日：2022-05-18

Applicant: Xilinx, Inc.

Inventor： Hari Bilash Dubey ,  Milind Goel ,  Venkata Siva Satya Prasad Babu Akurathi ,  Sabarathnam Ekambaram ,  Sasi Rama Subrahmanyam Lanka

IPC: H03K17/22 ,  H03K17/10 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K17/223 ,  H03K17/102 ,  H03K19/0013 ,  H03K19/00315

Abstract: A disclosed circuit arrangement detects the supply voltage level to the “device” (SoC, chip, SiP, etc.) and adjusts bias voltages to receiver and transmitter circuits of the device to levels suitable for the device in response to the supply voltage ramping-up during a power-on reset (“POR”) sequence. The circuitry holds the receiver output at a constant logic value while the supply voltage is ramping up and the POR signal is asserted. The disclosed circuitry also protects the transceiver as the voltage domain of the input signal is unknown and the voltage between any two terminals of a transistor of the transceiver cannot exceed a certain level.

公开(公告)号：US20230308384A1

公开(公告)日：2023-09-28

申请号：US17705087

申请日：2022-03-25

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Jaideep DASTIDAR ,  Jeffrey CUPPETT ,  Sagheer AHMAD

IPC: H04L49/109 ,  H04L45/24 ,  H04L45/74

CPC classification number: H04L45/24 ,  H04L45/74 ,  H04L49/109

Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.

公开(公告)号：US20230305949A1

公开(公告)日：2023-09-28

申请号：US17656236

申请日：2022-03-24

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema

IPC: G06F11/36 ,  G06F8/30

CPC classification number: G06F11/3688 ,  G06F8/311

Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.