公开(公告)号：WO1998008300A1

公开(公告)日：1998-02-26

申请号：PCT/US1997014472

申请日：1997-08-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ZUCKERMAN, Lawrence, H.

IPC: H03D03/00

CPC classification number: H03D3/00

Abstract: A very low intermediate frequency (IF) transceiver is described for use in a wireless LAN, cellular telephone, cordless telephone, and other radio transceiver applications. The transceiver preferably directly down-converts the RF signal to lower frequency such as a very low IF signal, which can be handled by transceiver components advantageously integrated with the communication control system such as an MAC or serial communications controller. Preferably, the very low IF signal is above peak modulation deviation and below the channel interval for the communication system. The very low IF signal may be up-converted so that the RF signal can be more reliably demodulated. Alternatively, the RF signal can be additionally converted to a second IF frequency before the very low IF frequency to reduce the effects of noise in the transceiver. Alternatively, an image rejection mixer circuit can be employed to provide some rejection selectivity for the adjacent channels on one side of the local oscillator. Alternatively, a phasing circuit can be added in the receiver front end to assist in the isolation of the local oscillator signal from the antenna.

Abstract translation: 描述了用于无线LAN，蜂窝电话，无绳电话和其他无线电收发器应用的非常低的中频（IF）收发器。 收发器优选地将RF信号直接下变频到较低频率，例如非常低的IF信号，其可以由有利地与诸如MAC或串行通信控制器的通信控制系统集成的收发器组件来处理。 优选地，非常低的IF信号高于通信系统的峰值调制偏差并低于信道间隔。 可以对非常低的IF信号进行上变频，从而可以更可靠地解调RF信号。 或者，RF信号可以在非常低的IF频率之前被额外地转换成第二IF频率，以减少收发器中的噪声的影响。 或者，可以采用镜像抑制混频器电路来为本地振荡器的一侧上的相邻信道提供一些拒绝选择性。 或者，可以在接收机前端添加定相电路以辅助从天线隔离本地振荡器信号。

公开(公告)号：WO1998007292A1

公开(公告)日：1998-02-19

申请号：PCT/US1997009546

申请日：1997-06-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MILLS, Andrew

IPC: H04Q11/04

CPC classification number: H04Q11/0428 ,  H04Q2213/13031 ,  H04Q2213/13034 ,  H04Q2213/1305 ,  H04Q2213/1309 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13107 ,  H04Q2213/13174 ,  H04Q2213/13176 ,  H04Q2213/13199 ,  H04Q2213/13202 ,  H04Q2213/13204 ,  H04Q2213/13205 ,  H04Q2213/13208 ,  H04Q2213/13209 ,  H04Q2213/13292 ,  H04Q2213/13335 ,  H04Q2213/13396

Abstract: communications device (200) is presented which is configured to provide selective signal processing at a "plain old telephone service" (POTS) interface, and ISDN U interface, or an ISDN S/T interface. A first POTS connector (208) allows the communications device to be connected to an analog POTS telephone line. A second ISDN U connector (209) allows the communications device to be connected to an ISDN network at an ISDN U interface point. A third ISDN S/T connector (213) allows the communications device to be connected to an ISDN network at an ISDN S/T interface point. A digital signal processing (DSP) core (202) performs: (i) analog modem functions via analog modem emulation when a POTS telephone line is connected to the POTS connector, or (ii) ISDN digital voice and data processing functions along with ISDN S/T and U interface functions when an ISDN line is connected to the ISDN U connector, or (iii) ISDN digital voice and data processing functions along with ISDN S/T interface functions when an ISDN line is connected to the ISDN S/T connector. Interface logic couples signals between the DSP core and the connectors. A digital data path multiplexer (204) coupled between the DSP core and the interface logic includes "autosense" logic (2220) which monitors signals received by the connector coupled to the telephone line and determines a data transfer mode based upon the received signals. The digital data path multiplexer provides the data transfer mode information to the DSP core, and the DSP core performs communications operations according to data transfer mode information.

Abstract translation: 通信设备（200）被配置为在“普通老式电话服务”（POTS）接口，ISDN U接口或ISDN S / T接口上提供选择性信号处理。 第一POTS连接器（208）允许通信设备连接到模拟POTS电话线路。 第二个ISDN U连接器（209）允许通信设备在ISDN U接口点连接到ISDN网络。 第三个ISDN S / T连接器（213）允许通信设备在ISDN S / T接口点连接到ISDN网络。 数字信号处理（DSP）核心（202）执行：（i）当POTS电话线连接到POTS连接器时，通过模拟调制解调器仿真进行模拟调制解调器功能，或（ii）ISDN数字语音和数据处理功能以及ISDN S 当ISDN线路连接到ISDN U连接器时，/ T和U接口功能，或（iii）当ISDN线路连接到ISDN S / T连接器时，ISDN数字语音和数据处理功能以及ISDN S / T接口功能 。 接口逻辑在DSP内核和连接器之间耦合信号。 耦合在DSP内核和接口逻辑之间的数字数据路径多路复用器（204）包括监视由耦合到电话线的连接器接收的信号的“自动检测”逻辑（2220），并根据接收的信号确定数据传输模式。 数字数据路径多路复用器将数据传输模式信息提供给DSP内核，DSP内核根据数据传输模式信息执行通信操作。

公开(公告)号：WO1998007261A1

公开(公告)日：1998-02-19

申请号：PCT/US1997003991

申请日：1997-03-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GROSSMAN, Leonid

IPC: H04L29/06

CPC classification number: H04L29/06

Abstract: A system and method for expediting data processing in a computer system including a network controller and a driver is disclosed. The method and system first provide a hardware structure. The hardware structure has a first plurality of fields and corresponds to a second structure. The second structure has a second plurality of fields. The first plurality of fields of the hardware structure has at least one field more than the second plurality of fields. The method and system then allow the driver to utilize the at least one extra field for increasing efficiency of data processing.

Abstract translation: 公开了一种用于在包括网络控制器和驱动器的计算机系统中加速数据处理的系统和方法。 该方法和系统首先提供硬件结构。 硬件结构具有第一多个字段并且对应于第二结构。 第二结构具有第二多个场。 硬件结构的第一多个字段具有比第二多个字段多的至少一个字段。 该方法和系统然后允许驾驶员利用至少一个额外的场来提高数据处理的效率。

公开(公告)号：WO1998007257A1

公开(公告)日：1998-02-19

申请号：PCT/US1997003797

申请日：1997-03-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KRISHNA, Gopal ,  KALKUNTE, Mohan

IPC: H04L12/413

CPC classification number: H04L12/413 ,  H04L12/44

Abstract: Delay times are modified in an Ethernet network device having captured the media channel by increasing the interframe spacing (IFS) between data packets. The modified IFS interval, increased by adding a delay interval to the minimum interpacket gap (IPG) interval after a predetermined number of consecutive successful transmissions, enables other network stations to transmit data during the deferral interval. The Ethernet network device maintains the modified IFS for a limited deferral interval, based upon a predetermined time interval or a number of successful transmissions by other network stations. Additional delay intervals may be added if the network station continues to exceed the predetermined number of consecutive successful transmissions. Hence, a network station can avoid capturing a network channel while ensuring access latencies.

Abstract translation: 在已经通过增加数据分组之间的帧间间隔（IFS）来捕获媒体信道的以太网网络设备中修改延迟时间。 通过在预定数量的连续成功传输之后将最小间隔间隔（IPG）间隔添加延迟间隔而增加的经修改的IFS间隔使其他网络站能够在延迟间隔期间发送数据。 以太网网络设备基于预定的时间间隔或其他网络站的成功传输的数量，在有限的延迟间隔内维护经修改的IFS。 如果网络站继续超过预定数量的连续成功传输，则可以添加额外的延迟时间间隔。 因此，网络站可以避免捕获网络信道，同时确保访问延迟。

公开(公告)号：WO1998006197A1

公开(公告)日：1998-02-12

申请号：PCT/US1997003578

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ROY, Rajat ,  KUO, Jerry, Chun-Jen ,  ANNADURAI, Andy, P.

IPC: H04L07/00

CPC classification number: H04L7/0083 ,  G06F1/08

Abstract: A circuit and method for switching between different frequency clock domains that are out of phase. The circuit has a select input for selecting which frequency domain is to be output, a first circuit associated with the first clock domain, and a second circuit associated with the second clock domain. The first and second circuits are responsive to the select input and work together to disengage the first clock before the second clock is engaged.

Abstract translation: 用于在不同频率的不同频率时钟域之间切换的电路和方法。 电路具有用于选择要输出哪个频域的选择输入，与第一时钟域相关联的第一电路以及与第二时钟域相关联的第二电路。 第一和第二电路响应于选择输入并一起工作以在第二时钟接合之前解除第一时钟。

公开(公告)号：WO1998003919A1

公开(公告)日：1998-01-29

申请号：PCT/US1997008921

申请日：1997-05-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BRIDGERS, K., Vincent ,  DRAKE, Michael ,  SCHUCKLE, Richard, W.

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0888 ,  G06F2212/206

Abstract: A computer system including a processor, a main memory and a cache memory uses tagging of various regions of memory to define and select caching properties of transfers between the processor and memory via the cache. The main memory contains not only standard random access memory (RAM) and read-only memory (ROM) but also memory-mapped input/output (I/O) sources. Tagging of the memory regions configures the regions for association with a particular set of caching properties. For example, a memory-mapped video I/O buffer may be tagged with a MM_IO_VBUF tag designating the caching properties of write-back cacheability with weak read/write ordering. Low-level operating system software, such as the Hardware Abstraction Language (HAL) interface of the Windows NT operating system or device driver software, initialize the memory regions, the cache and make symbolic associations between the memory regions and the cache. The cache, operating as directed by the memory tags, allows read and write operations that are used for performing various types of multimedia or signal processing operations including decompression, drawing operations, compression, mixing, and the like, which are performed on a virtually-cached multimedia drawing surface. The data for performing the multimedia or signal processing operations are either already located on the I/O surface or read from another storage location local to the processor or from an external processor, which is also cached and tagged as a special cached region. The processor executes operations acting on the cached data. When all operations are completely executed by the processor, only the cached memory regions are flushed using a flush instruction such as CFLSH[MM_IO_VBUF]. The flush instruction directs the cache to write back and invalidate the regions having the designated tag, here MM_IO_VBUF.

Abstract translation: 包括处理器，主存储器和高速缓冲存储器的计算机系统使用各种存储器区域的标记来定义和选择经由高速缓存处理器和存储器之间的传送的高速缓存属性。 主存储器不仅包含标准随机存取存储器（RAM）和只读存储器（ROM），还包含存储器映射的输入/输出（I / O）源。 内存区域的标记将区域配置为与一组特定的缓存属性相关联。 例如，存储器映射的视频I / O缓冲器可以用指定具有弱读/写顺序的回写高速缓存的缓存特性的MM_IO_VBUF标签来标记。 低级操作系统软件，例如Windows NT TM操作系统或设备驱动程序软件的硬件抽象语言（HAL）接口，初始化存储器区域，高速缓存并在存储器区域和高速缓存之间进行符号关联。 根据存储器标签的操作进行操作的高速缓存允许用于执行各种类型的多媒体或信号处理操作的读取和写入操作，包括解压缩，绘图操作，压缩，混合等， 缓存多媒体绘图面。 用于执行多媒体或信号处理操作的数据或者已经位于I / O表面上，或者从处理器本地的另一个存储位置读取或从外部处理器读取，外部处理器也被缓存并标记为特殊缓存区域。 处理器执行作用于缓存数据的操作。 当处理器完全执行所有操作时，仅使用诸如CFLSH [MM_IO_VBUF]之类的刷新指令刷新缓存的存储器区域。 刷新指令指示高速缓存回写并使具有指定标签的区域无效，这里是MM_IO_VBUF。

公开(公告)号：WO1998002804A1

公开(公告)日：1998-01-22

申请号：PCT/US1996011844

申请日：1996-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RAMAGOPAL, H., S. ,  HATTANGADI, Rajiv, M. ,  CHINNAKONDA, Muralidharan, S.

IPC: G06F09/38

CPC classification number: G06F9/3824 ,  G06F9/3834 ,  G06F9/3842

Abstract: A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Memory operations are selected from the load/store buffer for access to the data cache, including cases where the memory operation selected is subsequent in program order to a memory operation which is known to miss the data cache and is stored in the buffer. In this way, other memory operations that may be waiting for an opportunity to access the data cache may make such accesses, while the memory operations that have missed await an opportunity to make a main memory request. Memory operations that have missed are indicated by a miss bit being set, so that the mechanism which selects memory operations to access the data cache may ignore them until they become non-speculative.

Abstract translation: 提供了一个加载/存储缓冲区，允许加载存储器操作和存储存储器操作存储在其中。 从加载/存储缓冲器中选择存储器操作以访问数据高速缓存，包括所选择的存储器操作以程序顺序连续到已知丢失数据高速缓存并存储在缓冲器中的存储器操作的情况。 以这种方式，可能正在等待访问数据高速缓存的机会的其他存储器操作可以进行这样的访问，而错过的存储器操作等待有机会进行主存储器请求。 错过的存储器操作由设置的未命中位指示，从而选择存储器操作以访问数据高速缓存的机制可以忽略它们，直到它们变得不推测为止。

公开(公告)号：WO1998002799A1

公开(公告)日：1998-01-22

申请号：PCT/US1996011760

申请日：1996-07-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  RAMMOHAN, Narayan

Inventor： ADVANCED MICRO DEVICES, INC. ,  RAMMOHAN, Narayan

IPC: G06F09/30

CPC classification number: G06F9/382 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/3816 ,  G06F11/0721 ,  G06F11/0751

Abstract: An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start and end byte information associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scalable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects certain error conditions. Error information may be used by external logic to determine the proper course of action in light of the detected error.

Abstract translation: 公开了一种用于超标量微处理器的指令扫描单元。 指令扫描单元处理与多个相邻指令字节相关联的开始和结束字节信息。 开始字节信息和结束字节信息的处理是独立并行执行的，并且指令扫描单元产生多个扫描值，该扫描值标识多个连续指令字节内的有效指令。 另外，指令扫描单元是可扩展的。 可以并行操作多个指令扫描单元以处理较大的多个相邻指令字节。 此外，指令扫描单元检测到某些错误状况。 外部逻辑可以使用错误信息，以根据检测到的错误确定适当的动作过程。

公开(公告)号：WO1998002782A1

公开(公告)日：1998-01-22

申请号：PCT/US1997004868

申请日：1997-03-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SPENCE, Christopher, A.

IPC: G03F01/00

CPC classification number: G03F1/32

Abstract: A phase shift mask of the attenuating type for dense array image formation and large feature formation without printing sidelobes. For dense arrays, each zero phase E-field transmitting region (103) is surrounded by a 180 degree phase transmitting region (104) and an opaque non-transmitting region (105) is centrally located between each adjacent four zero phase regions. For large features, opaque material borders each corner and along long lines.

Abstract translation: 用于密集阵列图像形成的衰减类型的相移掩模和不打印旁瓣的大特征形成。 对于密集阵列，每个零相电场发射区域（103）由180度的相位发射区域（104）包围，而不透明非透射区域（105）位于每个相邻的四个零相位区域之间。 对于大的特征，不透明材料在每一个角落和沿着长条线边界。

公开(公告)号：WO1997050167A1

公开(公告)日：1997-12-31

申请号：PCT/US1997001332

申请日：1997-01-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LE, Binh, Quang ,  CHEN, Pau-Ling ,  HOLLMER, Shane

IPC: H02M03/07

CPC classification number: H02M3/073 ,  G05F3/205 ,  H01L27/0222

Abstract: A charge pump circuit having a fast rise time and reduced physical area is disclosed. The charge pump includes a plurality of stages having an non-uniform series of bootstrap capacitors. By using non-uniform capacitors at the various stages, charging rise time is enhanced while at the same time reducing the overall physical size of the charge pump.

Abstract translation: 公开了具有快速上升时间和减小的物理面积的电荷泵电路。 电荷泵包括具有不均匀系列自举电容器的多个级。 通过在各个阶段使用不均匀的电容器，增加充电上升时间，同时降低电荷泵的整体物理尺寸。