公开(公告)号：WO1998057438A1

公开(公告)日：1998-12-17

申请号：PCT/US1997023695

申请日：1997-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHENG, Yi ,  LIU, Zhenhua ,  RUNALDUE, Thomas, Jefferson

IPC: H04B03/14

CPC classification number: G01B7/02 ,  H03M1/367

Abstract: A cable length estimation circuit (110) for receiving an input MLT-3 signal provided through an arbitrary length cable (104) and providing a control signal to an equalizer (108) indicating the estimated length of the cable enabling the equalizer (108) to compensate for distortion of the MLT-3 signal resulting from the cable. The cable length estimation circuit (110) includes an edge rate detection circuit (400) for measuring the rate of change in voltage with respect to time during transitions of the MLT-3 signal to provide an indication of cable length. The cable length estimation circuit (110) can also include a digital averaging circuit (402) which provides an average value for signals from the edge rate detection circuit for a desired number of transitions of the MLT-3 signal. The cable length estimation (110) can also include a baseline wander detection circuit (404) which functions so that previous cable length estimations are provided when baseline wander is detected.

Abstract translation: 一种用于接收通过任意长度电缆（104）提供的输入MLT-3信号并向均衡器（108）提供控制信号的电缆长度估计电路（110），所述均衡器指示所述电缆的估计长度，使所述均衡器（108） 补偿由电缆产生的MLT-3信号的失真。 电缆长度估计电路（110）包括边缘速率检测电路（400），用于在MLT-3信号转变期间测量电压相对于时间的变化率，以提供电缆长度的指示。 电缆长度估计电路（110）还可以包括数字平均电路（402），该数字平均电路（402）为来自边缘速率检测电路的信号提供MLT-3信号的期望数量的转换的平均值。 电缆长度估计（110）还可以包括基线漂移检测电路（404），其用于在检测到基线漂移时提供先前的电缆长度估计。

公开(公告)号：WO1998056032A1

公开(公告)日：1998-12-10

申请号：PCT/US1997020192

申请日：1997-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  PAKERIASAMY, Saragarvani

IPC: H01L21/00

CPC classification number: H01L21/67333 ,  H01L2221/68313

Abstract: A mu BGA carrier for packing and shipping of a plurality of mu BGA packages is specially adapted for facilitating the inspection of the solder balls on the bottom surfaces of the mu BGA packages. The carrier consists of a tray member (12) having a plurality of first pockets (28) disposed therein for packing and storing the plurality of mu BGA packages, and a lid member (14) having a plurality of second pockets (40) formed therein. The second pockets are vertically aligned with corresponding ones of the plurality of first pockets in the tray member when the lid member is placed on top of the tray member. The carrier can be flipped upside-down so that when the tray member is removed the solder balls are facing upwardly to allow inspection of the same.

Abstract translation: 用于包装和运送多个mu BGA封装的mu BGA载体特别适用于便于对mu BGA封装的底表面上的焊球进行检查。 托架包括一个托盘构件（12），该托盘构件具有多个设置在其中的第一凹穴（28），用于堆放和储存多个mu BGA封装;以及盖构件（14），其具有形成在其中的多个第二凹穴（40） 。 当盖构件放置在托盘构件的顶部上时，第二袋与托盘构件中的多个第一袋中的相应的袋垂直对准。 载体可以颠倒翻转，使得当托盘构件被移除时，焊球面向上以允许对其进行检查。

公开(公告)号：WO1998033097A1

公开(公告)日：1998-07-30

申请号：PCT/US1997020034

申请日：1997-11-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LEVINSON, Harry, J.

IPC: G03F09/00

CPC classification number: G03F9/7026

Abstract: A method and apparatus wherein the height over the complete surface of interest on a wafer/material is scanned and mapped, using either a central or non-central focus system. The type of data gathered is similar to that which is normally acquired in operation of the particular focusing system indicative of the wafer/material surface height. The difference is that, according to the present invention, a much larger number of data points are sampled and then processed to provide improved focus information. These data are stored and used to calculate corrections in both the vertical position/height and tilt of the material/wafer for each exposure field, such as the areas (34) in Fig. 5b and 6b. The invention sorts out selected height data indicating periodic variations in surface height. Such data are normally not indicative of true wafer surface height variations, but instead are the result of periodic variations in wafer material composition caused by underlying structure relating to the particular circuitry. These periodic variations are distinguished from non-periodic variations, and are subtracted out of the total height measurement data to yield corrected surface height data. The present invention uses the corrected surface height data to calculate an optimum focus height for a given exposure area such as area (34).

Abstract translation: 一种方法和装置，其中使用中央或非中心聚焦系统扫描和映射在晶片/材料上的整个感兴趣的表面上的高度。 收集的数据类型与通常在指示晶片/材料表面高度的特定聚焦系统的操作中获得的类型相似。 不同之处在于，根据本发明，对更多数量的数据点进行采样，然后进行处理以提供改进的聚焦信息。 这些数据被存储并用于计算每个曝光场的材料/晶片的垂直位置/高度和倾斜度的校正，例如图1中的区域（34）。 5b和6b。 本发明对表示高度的周期性变化的所选高度数据进行排序。 这样的数据通常不表示真实的晶片表面高度变化，而是由与特定电路相关的底层结构引起的晶片材料组成的周期性变化的结果。 这些周期性变化与非周期性变化区分开，并从总高度测量数据中减去，以产生校正的表面高度数据。 本发明使用经校正的表面高度数据来计算诸如区域（34）的给定曝光区域的最佳聚焦高度。

公开(公告)号：WO1998028750A1

公开(公告)日：1998-07-02

申请号：PCT/US1997020819

申请日：1997-11-13

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

Inventor： ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED ,  CHEN, Johnny, C. ,  CHANG, Chung, K. ,  KUO, Tiao-Hua ,  AKAOGI, Takao

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C2216/22

Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation.

Abstract translation: 闪存器件分为两个或更多个存储体。 每个银行都包括一些行业。 每个扇区包括闪存单元。 每个存储体都有一个解码器，可选择性地从输入地址缓冲区或内部地址定序器接收由内部状态机控制的地址。 每个存储体的输出数据可以传送到读出读出放大器或验证读出放大器。 读出放大器连接到输出缓冲器，而验证放大器连接到状态机。 当一个银行收到一个写命令时，内部状态机接受控制并启动程序或擦除操作。 当一个银行忙于编程或擦除操作时，可以访问另一个存储体进行读取操作。

公开(公告)号：WO1998025205A1

公开(公告)日：1998-06-11

申请号：PCT/US1997023143

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  IRETON, Mark, A. ,  CHAMPAGNE, Gerald ,  MARLER, Corbett, A.

IPC: G06F11/20

CPC classification number: G06F9/328 ,  G06F8/66

Abstract: A system and method for performing software patches for embedded system devices in which the firmware of the system is included in non-alterable storage of the device. The patch mechanism provides a means for finding firmware errors, prototyping fixes to the errors and/or prototyping new functionality of the firmware of the embbeded system. The system comprises an embedded system device coupled to an external memory. The device includes a non-alterable memory, including firmware, coupled to a processor. The device further includes a relatively small amount of patch RAM within the device also coupled to the processor. The patches are loaded from the external memory into the patch RAM. The device further includes a means for determining if one or more patches are to be applied. If the device detects a patch to be applied, the system loads the patch from the external memory into the patch RAM. The device also includes a breakpoint register. When the value of the program counter of the processor equals the value in the breakpoint register, a patch insertion occurs, i.e., the processor deviates from executing firmware to executing patch instructions. Preferably, the embedded system device comprises a single integrated circuit. The processor may include a plurality of breakpoint registers. The patch may be encrypted for increased security. Multiple patches may be chained together, and run-time patch replacement is contemplated.

Abstract translation: 一种用于对嵌入式系统设备执行软件补丁的系统和方法，其中所述系统的固件被包括在所述设备的不可更改存储器中。 补丁机制提供了一种用于查找固件错误，原型修复错误和/或原型化嵌入式系统固件的新功能的方法。 该系统包括耦合到外部存储器的嵌入式系统设备。 该设备包括耦合到处理器的不可更改的存储器，包括固件。 该设备还包括在设备内的相对少量的补丁RAM，其也耦合到处理器。 补丁从外部存储器加载到补丁RAM中。 该装置还包括用于确定是否应用一个或多个补丁的装置。 如果设备检测到要应用的补丁，则系统将补丁从外部存储器加载到补丁RAM中。 该器件还包括一个断点寄存器。 当处理器的程序计数器的值等于断点寄存器中的值时，会发生补丁插入，即处理器从执行固件偏离到执行补丁指令。 优选地，嵌入式系统设备包括单个集成电路。 处理器可以包括多个断点寄存器。 可以加密补丁以增加安全性。 多个补丁可以链接在一起，并且考虑运行时补丁更换。

公开(公告)号：WO1998025183A1

公开(公告)日：1998-06-11

申请号：PCT/US1997023139

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F07/20

CPC classification number: G03F7/70058 ,  G03F7/70591 ,  G03F7/70891

Abstract: A method of inspecting a lens (16) includes projecting a first amount of radiation through a first test pattern (42, 44) and the lens to provide a first lens error associated with a first heating of the lens, projecting a second amount of radiation through a second test pattern (52, 54) and the lens to provide a second lens error associated with a second heating of the lens, and using the first and second lens errors to provide image displacement data that varies as a function of heating the lens. In this manner, corrections can be made for localized lens heating that is unique to a given reticle. The method is well-suited for photolithographic systems such as step and repeat systems.

Abstract translation: 检查透镜（16）的方法包括：通过第一测试图案（42,44）和透镜投射第一量的辐射，以提供与透镜的第一加热相关联的第一透镜误差，投射第二量的辐射 通过第二测试图案（52,54）和透镜提供与透镜的第二加热相关联的第二透镜误差，并且使用第一和第二透镜误差来提供作为加热透镜的函数而变化的图像位移数据 。 以这种方式，可以对给定掩模版特有的局部透镜加热进行校正。 该方法非常适合于光刻系统，如步进和重复系统。

公开(公告)号：WO1998023071A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021469

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  SCHINZLEIN, Paul

IPC: H04L27/227

CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A digital loop filter in the carrier-recovery loop of a digital communications receiver. The recovery loop is a PLL that keeps the receiver oscillator locked to the carrier wave, and the loop filter provides control over the PLL's frequency response by conditioning an error signal that is fed back to the receiver oscillator. In the present invention, the error signal is a digital signal, and the loop filter is implemented in digital hardward. With this implementation the characteristics of the loop filter are determined by logic design rather than by physical features of analog components, thereby giving this filter a more precise function than one with analog integrators. This implementation is also immune to the low tolerances typical of the manufacturing process for analog devices (especially on monolithic circuits), and is more easily adjusted than its analog counterparts. Two gain coefficients characterize the loop filter in the present invention. These gain coefficients are chosen to be powers of two, simplifying the process of multiplying them with the digital error signal. The gain coefficients are read from a memory, making the loop filter easily programmable. By changing the gain coefficients during operation of the receiver, the carrier-recovery loop can be placed in one of the several operating modes, including acquisition, tracking, and hold. The receiver can be configured with the appropriate values of the gain coefficients for each operating mode during the initial assembly and during subsequent reconfigurations.

Abstract translation: 数字通信接收机的载波恢复回路中的数字环路滤波器。 恢复环路是将接收器振荡器锁定到载波的PLL，环路滤波器通过调节反馈到接收机振荡器的误差信号来提供对PLL频率响应的控制。 在本发明中，误差信号是数字信号，环路滤波器以数字硬件方式实现。 通过这种实现，环路滤波器的特性由逻辑设计而不是模拟组件的物理特性决定，从而使得该滤波器比具有模拟积分器的功能更精确。 该实现也不受模拟器件（特别是单片电路）的制造工艺典型的低容差的影响，并且比其模拟器件更容易调整。 两个增益系数表征本发明中的环路滤波器。 这些增益系数被选为2的幂，简化了与数字误差信号相乘的过程。 从存储器读取增益系数，使得环路滤波器易于编程。 通过在接收机操作期间改变增益系数，载波恢复回路可以放置在几种操作模式之一，包括采集，跟踪和保持。 可以在初始组装期间和随后的重新配置期间，为每个操作模式的接收机配置适当的增益系数值。

公开(公告)号：WO1998022877A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021506

申请日：1997-11-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HEWITT, Larry, D.

IPC: G06F11/30

CPC classification number: G06F11/3027 ,  G06F11/3079 ,  G06F13/423 ,  G06F2201/81 ,  G06F2201/88

Abstract: An arrangement for monitoring clock frequency variations on a peripheral bus (211) is provided to improve operations of the peripheral device (118, 119) despite changes in the clock frequency. In one aspect of the arrangement, a processing unit (101) is coupled to a host bus (103) which in turn is coupled to a peripheral bus which is coupled to a peripheral device. A monitoring arrangement (121) is provided which detects a change in the clock frequency of the peripheral bus and determines if the frequency change exceeds a threshold associated with the peripheral device. If the threshold is exceeded, the peripheral device is informed that the clock frequency of the peripheral bus has changed. A peripheral device operating at different operating levels may use the information from the monitoring arrangement to alter the operating level of the peripheral device to conform to the new bus clock frequency.

Abstract translation: 提供了用于监视外围总线（211）上的时钟频率变化的装置，以便尽管时钟频率的改变来改善外围设备（118,119）的操作。 在该装置的一个方面，处理单元（101）耦合到主机总线（103），主机总线（103）又耦合到耦合到外围设备的外围总线。 提供了一种监视装置（121），其检测外围总线的时钟频率的变化，并确定频率变化是否超过与外围设备相关联的阈值。 如果超过阈值，则通知外围设备外围总线的时钟频率已经改变。 在不同操作级别操作的外围设备可以使用来自监视装置的信息来改变外围设备的操作级别以符合新的总线时钟频率。

公开(公告)号：WO1998014956A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017635

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WENDELL, Dennis, L.

IPC: G11C29/00

CPC classification number: G11C29/026 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.

Abstract translation: 公开了存储器阵列测试和表征能力，其允许存储器单元，位线和读出放大器的DC表征。 提供行解码器，其包括静态字线选择信号以禁止行解码器内的自复位逻辑，并允许字线在用户控制的时间长度上保持有效。 模拟字线驱动能力允许有源字线被驱动到用户可控的模拟电平。 直接访问一对位线由多路复用器提供，多路复用器被静态解码以将一对隔离终端耦合到解码列内的相应位线。 这允许在解码列内和/或两个位线电流中的每个位线上施加直流电压电平以被感测。 为存储器阵列提供单独的电源连接，其允许以与电路的其余部分不同的电源电压操作存储器阵列。 通过将这些特征中的一个或多个一起使用，可以执行存储器阵列的若干测试，包括表征存储器单元的DC传递函数，存储器阵列的待机功率，存储器单元的静态噪声容限， 作为存储单元电源电压的函数的存储器单元的粒子敏感性，位线读出放大器的偏移电压等。

公开(公告)号：WO1998014950A1

公开(公告)日：1998-04-09

申请号：PCT/IB1997001388

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WENDELL, Dennis, Lee ,  HOLST, John, Christian

IPC: G11C08/00

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995 ,  Y02D10/13

Abstract: A highly suitable power conservation technique involves extending multiple word lines over a memory array row and connecting a portion of the memory cells of the memory array row to each of the word lines. Power is supplied only to the portion of the memory cells that is accessed, eliminating the static power consumption of the non-accessed memory cells. By connecting multiple word lines to select a portion of a memory row, a column address of the memory is mapped into a row decode space. Multiple metal layers in a complex integrated circuit may be exploited to form cache block select lines using multiple word lines per cell row. A storage includes a plurality of storage cells arranged in an array of rows and columns, a plurality of bit lines connecting the array of storage cells into columns, and a plurality of word lines connecting the array of storage cells into rows. The plurality of word lines include multiple word lines for a single row of the plurality of rows so that multiple portions of the storage cells in the single row are addressed by corresponding multiple word lines.

Abstract translation: 高度合适的功率保存技术涉及在存储器阵列行上延伸多个字线并将存储器阵列行的存储单元的一部分连接到每个字线。 电源仅被提供给所访问的存储器单元的部分，消除了非存取存储器单元的静态功耗。 通过连接多个字线来选择存储器行的一部分，存储器的列地址被映射到行解码空间。 可以利用复杂集成电路中的多个金属层来形成每个单元行使用多个字线的高速缓存块选择线。 存储器包括布置成行和列阵列的多个存储单元，将存储单元阵列连接成列的多个位线以及将存储单元阵列连接成行的多个字线。 多个字线包括用于多行的单行的多个字线，使得单行中的存储单元的多个部分由相应的多个字线寻址。