公开(公告)号：WO2010077884A3

公开(公告)日：2010-09-30

申请号：PCT/US2009068114

申请日：2009-12-15

Applicant: INTEL CORP ,  SHEAFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  COHEN EHUD ,  MARGULIS OLEG

Inventor： SHEAFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  COHEN EHUD ,  MARGULIS OLEG

IPC: G06F12/08 ,  G06F9/06

CPC classification number: G06F9/3834 ,  G06F9/30076 ,  G06F9/3838 ,  G06F11/0715 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/3017 ,  G06F11/3037 ,  G06F11/3089 ,  G06F11/3471 ,  G06F12/0831 ,  G06F12/084 ,  G06F2201/885

Abstract: A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.

Abstract translation: 这里描述了一种用于提供用于硬件属性以支持事务执行的存储器模型的方法和装置。 在遇到诸如加载读取监视器，写入监视器或缓冲属性的测试监视器操作的硬件属性的负载时，响应于指示硬件属性已经丢失的丢失字段而发出故障。 此外，基于地址依赖性和访问类型依赖性，为属性访问操作提供依赖操作，例如阻塞和转发。 因此，在存储器模型中允许和限制属性丢失和测试的不同场景。

公开(公告)号：WO2010065413A3

公开(公告)日：2010-08-26

申请号：PCT/US2009065892

申请日：2009-11-25

Applicant: QUALCOMM INC ,  JAYARAMAN SATYA ,  ABHYANKAR SACHIN ,  JONG ALEX KWANG-HO ,  HIGGINS RICHARD ALFRED

Inventor： JAYARAMAN SATYA ,  ABHYANKAR SACHIN ,  JONG ALEX KWANG-HO ,  HIGGINS RICHARD ALFRED

IPC: G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/3476 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/885

Abstract: A dynamic performance profiler is operable to receive, in substantially real-time, raw performance data from a testing platform. A software-based image is executing on a target hardware platform (e.g., either simulated or actual) on the testing platform, and the testing platform monitors such execution to generate corresponding raw performance data, which is communicated, in substantially real-time, as it is generated during execution of the software-based image to a dynamic profiler. The dynamic profiler may be configured to archive select portions of the received raw performance data to data storage. As the raw performance data is received, the dynamic profiler analyzes the data to determine whether the performance of the software-based image on the target hardware platform violates a predefined performance constraint. When the performance constraint is violated, the dynamic profiler archives a portion of the received raw performance.

Abstract translation: 动态性能分析器可操作以基本上实时地从测试平台接收原始性能数据。 基于软件的图像在测试平台上的目标硬件平台（例如，模拟的或实际的）上执行，并且测试平台监视这种执行以生成相应的原始性能数据，其基本上实时地传送，如同 它是在将基于软件的映像执行到动态分析器时生成的。 动态分析器可以被配置成将接收到的原始演奏数据的选择部分归档到数据存储器。 当接收到原始性能数据时，动态分析器分析数据以确定目标硬件平台上基于软件的映像的性能是否违反预定义的性能约束。 违反性能约束时，动态分析器会归档接收到的原始性能的一部分。

公开(公告)号：WO2010023533A2

公开(公告)日：2010-03-04

申请号：PCT/IB2009/006631

申请日：2009-08-24

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (publ) ,  WALKER, Anthony, Dean

Inventor： WALKER, Anthony, Dean

IPC: G06F17/50 ,  G06F11/34

CPC classification number: G06F17/5022 ,  G06F11/3409 ,  G06F11/3461 ,  G06F11/349 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

Abstract: An efficient, cycle-accurate processor execution simulator models a target processor by executing a program execution image comprising instructions having run-time dependencies resolved by execution on an existing processor compatible with the target processor. The instructions may have been executed upon a processor in an I/O environment too complex to model. In one embodiment, the simulator executes instructions that were directly executed on a processor. In another embodiment, a markup engine alters a compiled program image, with reference to instructions executed on a processor, to remove run-time dependencies. The marked up program image is then executed by the simulator. The processor execution simulator includes an update engine operative to cycle-accurately simulate instruction execution, and a communication engine operative to model each communication bus of the target processor.

Abstract translation: 有效的，循环精确的处理器执行模拟器通过执行程序执行图像来建模目标处理器，该程序执行图像包括具有通过在与目标处理器兼容的现有处理器上的执行而被解析的运行时依赖性的指 指令可能已经在I / O环境中的处理器上执行过于复杂，无法建模。 在一个实施例中，模拟器执行在处理器上直接执行的指令。 在另一个实施例中，标记引擎参照在处理器上执行的指令来改变已编译的程序图像，以去除运行时依赖性。 标记的程序图像然后由模拟器执行。 处理器执行模拟器包括可操作以循环精确地模拟指令执行的更新引擎和可操作以对目标处理器的每个通信总线进行建模的通信引擎。

公开(公告)号：WO2009000625A1

公开(公告)日：2008-12-31

申请号：PCT/EP2008/057016

申请日：2008-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  LUICK, David, Arnold ,  VITALE, Philip, Lee

Inventor： LUICK, David, Arnold ,  VITALE, Philip, Lee

IPC: G06F11/34

CPC classification number: G06F11/3409 ,  G06F11/349 ,  G06F11/3495 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: The present invention related to computer architecture, and more specifically to evaluating performance of processors. A performance monitor may be placed in an L2 cache nest of a processor. The performance monitor may monitor L2 cache accesses and receive performance data from one or more processor cores over a bus coupling the processor cores with the L2 cache nest. In one embodiment the bus may include additional lines for transferring performance data from the processor cores to the performance monitor.

Abstract translation: 本发明涉及计算机体系结构，更具体地说是用于评估处理器的性能。 性能监视器可以放置在处理器的L2高速缓存嵌套中。 性能监视器可以监视L2高速缓存访​​问，并通过将处理器核与L2高速缓存嵌套耦合的总线从一个或多个处理器核接收性能数据。 在一个实施例中，总线可以包括用于将性能数据从处理器核传递到性能监视器的附加线。

公开(公告)号：WO2008141873A1

公开(公告)日：2008-11-27

申请号：PCT/EP2008/054540

申请日：2008-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  LICHTENAU, Cedric ,  PFLUEGER, Thomas ,  WEISS, Ulrich ,  GEMMEKE, Tobias

Inventor： LICHTENAU, Cedric ,  PFLUEGER, Thomas ,  WEISS, Ulrich ,  GEMMEKE, Tobias

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/3808 ,  G06F9/3844 ,  G06F11/3409 ,  G06F2201/88 ,  G06F2201/885 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/34

Abstract: The invention relates to a method for power management of a microprocessor characterized by the use of a workload prediction method for adaptation of the power consumption of said microprocessor to workload during program execution. The method is characterized by measuring at least microprocessor utilization between two branch instructions. This is achieved by using a utilization history table similar to a branch history that profiles the microprocessor utilization during execution and is used for subsequent execution of the same code segment.

Abstract translation: 本发明涉及一种微处理器的电源管理方法，其特征在于使用工作负载预测方法，用于在程序执行期间使所述微处理器的功耗适应工作负载。 该方法的特征在于至少测量两个分支指令之间的微处理器利用率。 这通过使用类似于在执行期间描述微处理器利用的分支历史的利用历史表来实现，并且用于后续执行相同的代码段。

公开(公告)号：WO2005065205A3

公开(公告)日：2007-03-08

申请号：PCT/US2004042313

申请日：2004-12-15

Applicant: MICRON TECHNOLOGY INC ,  JEDDELOH JOSEPH M

Inventor： JEDDELOH JOSEPH M

IPC: G06F12/02 ,  G06F12/00 ,  G06F13/16

CPC classification number: G06F13/161 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/3485 ,  G06F11/349 ,  G06F13/1694 ,  G06F2201/88 ,  G06F2201/885

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, read rate, number of read requests, write rate, number of write requests, rate or percentage of memory bus utilization, local hub request rate or number, and/or remote hub request rate or number.

Abstract translation: 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括跟踪一个或多个系统度量的至少一个性能计数器，例如页面命中率，预取命中的数量或百分比，高速缓存命中率或百分比，读取速率，读取请求数，写入速率，写入速率， 写请求，速率或百分比的内存总线利用率，本地集线器请求速率或数量，和/或远程集线器请求速率或数量。

公开(公告)号：WO2006131437A2

公开(公告)日：2006-12-14

申请号：PCT/EP2006062341

申请日：2006-05-16

Applicant: IBM ,  IBM UK ,  BARSNESS ERIC LAWRENCE ,  MAJD MAHDAD ,  SANTOSUOSSO JOHN MATTHEW

Inventor： BARSNESS ERIC LAWRENCE ,  MAJD MAHDAD ,  SANTOSUOSSO JOHN MATTHEW

CPC classification number: G06F11/3495 ,  G06F9/50 ,  G06F9/5083 ,  G06F11/3433 ,  G06F2201/86 ,  G06F2201/875 ,  G06F2201/885 ,  H04L67/1002 ,  H04L67/1008 ,  H04L67/1034 ,  H04L67/125 ,  H04L69/40

Abstract: A load balancer detects a server failure, and sends a failure notification message to the remaining servers. In response, one or more of the remaining servers may autonomically adjust their configuration parameters, thereby allowing the remaining servers to better handle the increased load caused by the server failure. One or more of the servers may also include a performance measurement mechanism that measures performance before and after an autonomic adjustment of the configuration parameters to determine whether and how much the autonomic adjustments improved the system performance. In this manner server computer systems may autonomically compensate for the failure of another server computer system that was sharing the workload.

Abstract translation: 负载均衡器检测到服务器故障，并向剩余的服务器发送故障通知消息。 作为响应，一个或多个剩余服务器可以自主地调整其配置参数，从而允许其余服务器更好地处理由服务器故障引起的增加的负载。 一个或多个服务器还可以包括性能测量机制，其在配置参数的自主调整之前和之后测量性能，以确定自主调整是否以及多少改善系统性能。 以这种方式，服务器计算机系统可以自主地补偿共享工作负载的另一服务器计算机系统的故障。

公开(公告)号：WO2005064472A2

公开(公告)日：2005-07-14

申请号：PCT/US2004/042484

申请日：2004-12-17

Applicant: UNISYS CORPORATION

Inventor： HOFFMAN, Phillip, M. ,  REIST, Randolph, C. ,  STELL, Jeffery, A. ,  PARAGAS, Jessica, A. ,  THOMPSON, James, W.

IPC: G06F11/28

CPC classification number: G06F11/3409 ,  G06F11/3466 ,  G06F2201/87 ,  G06F2201/885

Abstract: A system and method for metering usage of a data processing system and scaling system performance is disclosed. In one embodiment, an authorization key is purchased that specifies both a baseline performance level and a ceiling performance level. After the key is installed on the data processing system, the system performance level is monitored and averaged over predetermined time periods. The customer is charged on a “pas-as-you-go” basis for any time periods during which the average performance level exceeds the baseline performance level. Performance of the data processing system is not allowed to exceed the ceiling level obtained with the authorization key. In one embodiment, the baseline level may be set to zero so that all performance consumption is purchased by the customer as it is utilized. A report may be generated that includes data upon which analysis of the measured processor utilization data may be performed.

Abstract translation: 公开了一种用于计量数据处理系统的使用和缩放系统性能的系统和方法。 在一个实施例中，购买了指定基准性能水平和最高性能水平的授权密钥。 在密钥安装在数据处理系统上之后，系统性能级别将在预定时间段内进行监控和平均。 在平均绩效水平超过基准绩效水平的任何时间段内，客户都将按照“即时取消”进行收费。 数据处理系统的性能不允许超过授权密钥获得的最高级别。 在一个实施例中，可以将基线水平设置为零，使得在所使用的情况下，客户购买所有的性能消耗。 可以生成包括可以对其测量的处理器利用数据进行分析的数据的报告。

公开(公告)号：WO02054245A2

公开(公告)日：2002-07-11

申请号：PCT/US0144083

申请日：2001-11-26

Applicant: INTEL CORP

Inventor： CRANFORD MICHAEL ,  RODGERS SCOTT D ,  KALAFATIS STAVOS

IPC: G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: A method and apparatus for monitoring the performance characteristics of a multithreaded processor (10) executing instructions from two or more threads simultaneously. Event detectors detect the occurrence of specific processor events (20) during the execution of instructions from threads of a multithreaded processor. Specialized event select controls registers (30) are programmed to control the selection, masking and qualifying of events to be monitored. Events arequalified according to their thread ID and thread current privilege level (CPL). Each event that is qualified is counted by one of several programmable event counters (70) that keep track of all processor events being monitored. The contents of the event counters can then be accessed and sampled via a program instruction.

Abstract translation: 一种用于监视同时执行来自两个或多个线程的指令的多线程处理器（10）的性能特征的方法和装置。 在从多线程处理器的线程执行指令期间，事件检测器检测特定处理器事件（20）的发生。 专门的事件选择控制寄存器（30）被编程为控制要监视的事件的选择，屏蔽和限定。 事件根据其线程ID和线程当前权限级别（CPL）进行资格评估。 每个符合条件的事件都由几个可编程事件计数器（70）之一进行计数，这些可编程事件计数器（70）跟踪所有被监视的处理器事件 然后可以通过程序指令访问和采样事件计数器的内容。

公开(公告)号：WO01086447A3

公开(公告)日：2002-03-21

申请号：PCT/US2001/009872

申请日：2001-03-28

IPC: G06F11/34

CPC classification number: G06F11/3409 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: A performance monitor system includes a core processor (115), a core processor associated device, such as a cache (123), and first logic, such as performance logic (127). The core processor (115) is operable to execute information. The core processor associated device provides a first signal (CACHE_PERF), which defines performance of the core processor associated device (123) during operation of the core processor (115). The first logic (127) is coupled to the core processor associated device (123) and monitors the first signal (CACHE_PERF) in response to a second signal (WPT0,1), which defines a match of user-settable attributes associated with the operation of the core processor (115).

Abstract translation: 性能监视器系统包括核心处理器（115），诸如高速缓存（123）的核心处理器关联设备以及诸如性能逻辑（127）之类的第一逻辑。 核心处理器（115）可操作以执行信息。 核心处理器相关设备提供在核心处理器（115）的操作期间定义核心处理器相关设备（123）的性能的第一信号（CACHE_PERF）。 第一逻辑（127）耦合到核心处理器相关设备（123）并且响应于第二信号（WPT0,1）监视第一信号（CACHE_PERF），其定义与操作相关联的用户可设置属性的匹配 的核心处理器（115）。