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    Asynchronous control transfer
    1.
    发明专利
    Asynchronous control transfer 有权
    异步控制传输

    公开(公告)号：JP2008165793A

    公开(公告)日：2008-07-17

    申请号：JP2007334336

    申请日：2007-12-26

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： NEWBURN CHRIS J ,  RODGERS SCOTT D ,  KNIGHT ROBERT P ,  ITTAI ANATI ,  CHINYA GAUTHAM N

    IPC: G06F9/48

    CPC classification number: G06F9/542

    Abstract: PROBLEM TO BE SOLVED: To provide a method and device for performing asynchronous control transfer.
    SOLUTION: According to one embodiment, when an event (such as an event on an architecture) occurs, a service routine data block (SRDB) is accessed to obtain an address of a yield service routine. Another embodiment is also described.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于执行异步控制传送的方法和装置。 解决方案：根据一个实施例，当发生事件（诸如架构上的事件）时，访问服务例程数据块（SRDB）以获得产出服务例程的地址。 还描述了另一个实施例。 版权所有（C）2008，JPO＆INPIT

    BY THREAD ID AND THREAD PRIVILEGE LEVEL
    2.
    发明申请
    BY THREAD ID AND THREAD PRIVILEGE LEVEL 审中-公开
    通过螺纹编号和螺纹特殊等级

    公开(公告)号：WO02054245A2

    公开(公告)日：2002-07-11

    申请号：PCT/US0144083

    申请日：2001-11-26

    Applicant: INTEL CORP

    Inventor： CRANFORD MICHAEL ,  RODGERS SCOTT D ,  KALAFATIS STAVOS

    IPC: G06F11/34

    CPC classification number: G06F11/3466 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

    Abstract: A method and apparatus for monitoring the performance characteristics of a multithreaded processor (10) executing instructions from two or more threads simultaneously. Event detectors detect the occurrence of specific processor events (20) during the execution of instructions from threads of a multithreaded processor. Specialized event select controls registers (30) are programmed to control the selection, masking and qualifying of events to be monitored. Events arequalified according to their thread ID and thread current privilege level (CPL). Each event that is qualified is counted by one of several programmable event counters (70) that keep track of all processor events being monitored. The contents of the event counters can then be accessed and sampled via a program instruction.

    Abstract translation: 一种用于监视同时执行来自两个或多个线程的指令的多线程处理器（10）的性能特征的方法和装置。 在从多线程处理器的线程执行指令期间，事件检测器检测特定处理器事件（20）的发生。 专门的事件选择控制寄存器（30）被编程为控制要监视的事件的选择，屏蔽和限定。 事件根据其线程ID和线程当前权限级别（CPL）进行资格评估。 每个符合条件的事件都由几个可编程事件计数器（70）之一进行计数，这些可编程事件计数器（70）跟踪所有被监视的处理器事件 然后可以通过程序指令访问和采样事件计数器的内容。

    QUALIFICATION OF EVENT DETECTION BY THREAD ID AND THREAD PRIVILEGE LEVEL
    3.
    发明申请
    QUALIFICATION OF EVENT DETECTION BY THREAD ID AND THREAD PRIVILEGE LEVEL 审中-公开
    通过螺纹识别和螺纹特性水平检查事件的资格

    公开(公告)号：WO02054245A8

    公开(公告)日：2002-09-12

    申请号：PCT/US0144083

    申请日：2001-11-26

    Applicant: INTEL CORP

    Inventor： CRANFORD MICHAEL ,  RODGERS SCOTT D ,  KALAFATIS STAVOS

    IPC: G06F11/34

    CPC classification number: G06F11/3466 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

    Abstract: A method and apparatus for monitoring the performance characteristics of a multithreaded processor (10) executing instructions from two or more threads simultaneously. Event detectors detect the occurrence of specific processor events (20) during the execution of instructions from threads of a multithreaded processor. Specialized event select controls registers (30) are programmed to control the selection, masking and qualifying of events to be monitored. Events arequalified according to their thread ID and thread current privilege level (CPL). Each event that is qualified is counted by one of several programmable event counters (70) that keep track of all processor events being monitored. The contents of the event counters can then be accessed and sampled via a program instruction.

    Abstract translation: 一种用于监视同时执行来自两个或多个线程的指令的多线程处理器（10）的性能特征的方法和装置。 在从多线程处理器的线程执行指令期间，事件检测器检测特定处理器事件（20）的发生。 专门的事件选择控制寄存器（30）被编程为控制要监视的事件的选择，屏蔽和限定。 事件根据其线程ID和线程当前权限级别（CPL）进行资格认证。 每个符合条件的事件都由几个可编程事件计数器（70）之一进行计数，这些可编程事件计数器（70）跟踪所有被监视的处理器 然后可以通过程序指令访问和采样事件计数器的内容。

    SYSTEM, METHOD, AND APPARATUS FOR A CACHE FLUSH OF A RANGE OF PAGES AND TLB INVALIDATION OF A RANGE OF ENTRIES
    4.
    发明申请
    SYSTEM, METHOD, AND APPARATUS FOR A CACHE FLUSH OF A RANGE OF PAGES AND TLB INVALIDATION OF A RANGE OF ENTRIES 审中-公开
    系统，方法和装置，用于高速缓存页面和TLB无效的入口范围

    公开(公告)号：WO2011087589A3

    公开(公告)日：2011-10-27

    申请号：PCT/US2010058236

    申请日：2010-11-29

    Applicant: INTEL CORP ,  DIXON MARTIN G ,  RODGERS SCOTT D

    Inventor： DIXON MARTIN G ,  RODGERS SCOTT D

    IPC: G06F12/08 ,  G06F9/312

    CPC classification number: G06F12/1009 ,  G06F12/0891 ,  G06F12/1027 ,  G06F2212/1016

    Abstract: Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor.

    Abstract translation: 描述了用于执行多个高速缓存行的刷新和/或多个翻译后备缓冲器（TLB）条目的无效的系统，方法和装置。 在一种这样的方法中，为了冲洗处理器的多个高速缓存行，包括指示处理器的多个高速缓存行将被刷新的第一字段的单个指令并且响应于单个指令，刷新多个高速缓存 处理器的行。

    UNIT OF MICROPROCESSOR FOR GENERATING OF ADDRESS WITH SEGMENT ADDRESSES
    7.
    发明专利
    UNIT OF MICROPROCESSOR FOR GENERATING OF ADDRESS WITH SEGMENT ADDRESSES 未知

    公开(公告)号：SK995A3

    公开(公告)日：1995-08-09

    申请号：SK995

    申请日：1995-01-04

    Applicant: INTEL CORP

    Inventor： HUCK KAMLA P ,  RODGERS SCOTT D ,  GLEW ANDREW F

    IPC: G06F9/34 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F9/00

    Abstract: A microprocessor comprising an execution unit for performing arithmetic functions, a fetch unit for determining which entry is to be accessed, an issue unit for accessing the entry from storage in a memory, and an address generation unit for generating an address for that entry. Portions of the base and limit values used for generating the address are stored in separate segments. These separate portions are rearranged so as to form a segment having contiguous base and limit bits. The contiguous base and limit values are then stored in a register file. Copies of the base and limit are stored in control registers and broadcast to other units. Furthermore, a resettable null bit is stored in another register. In addition, the AGU includes a means for selecting a particular field of the register file and performing read/write operations on the selected file.

    9.
    发明专利
    未知

    公开(公告)号：BR0116654A

    公开(公告)日：2005-08-16

    申请号：BR0116654

    申请日：2001-11-26

    Applicant: INTEL CORP

    Inventor： CRANFORD MICHAEL ,  RODGERS SCOTT D ,  KALAFATIS STAVOS ,  SPRUNT H M BRINKLEY

    IPC: G06F11/34

    Abstract: A method and apparatus for monitoring the performance characteristics of a multithreaded processor executing instructions from two or more threads simultaneously. Event detectors detect the occurrence of specific processor events during the execution of instructions from threads of a multithreaded processor. Specialized event select control registers are programmed to control the selection, masking and qualifying of events to be monitored. Events are qualified according to their thread ID and thread current privilege level (CPL). Each event that is qualified is counted by one of several programmable event counters that keep track of all processor events being monitored. The contents of the event counters can then be accessed and sampled via a program instruction.

    Qualification of event detection by thread id and thread privilege level
    10.
    发明专利
    Qualification of event detection by thread id and thread privilege level 未知

    公开(公告)号：AU2002217850A1

    公开(公告)日：2002-07-16

    申请号：AU2002217850

    申请日：2001-11-26

    Applicant: INTEL CORP

    Inventor： CRANFORD MICHAEL ,  RODGERS SCOTT D ,  KALAFATIS STAVOS ,  SPRUNT H M BRINKLEY

    IPC: G06F11/34

    Abstract: A method and apparatus for monitoring the performance characteristics of a multithreaded processor executing instructions from two or more threads simultaneously. Event detectors detect the occurrence of specific processor events during the execution of instructions from threads of a multithreaded processor. Specialized event select control registers are programmed to control the selection, masking and qualifying of events to be monitored. Events are qualified according to their thread ID and thread current privilege level (CPL). Each event that is qualified is counted by one of several programmable event counters that keep track of all processor events being monitored. The contents of the event counters can then be accessed and sampled via a program instruction.

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