公开(公告)号：EP1321981A3

公开(公告)日：2006-10-11

申请号：EP02257811.6

申请日：2002-11-12

Applicant: STMicroelectronics, Inc.

Inventor： Siegel, Harry M. ,  Lane, Fred P. ,  Evans, Richard P.

IPC: G06K9/00 ,  G06K9/20

CPC classification number: G06K9/00053 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A touch-sensitive semiconductor chip having a physical interface to the environment, where the surface of the physical interface is coated with a fluorocarbon polymer. The polymer is highly scratch resistant and has a characteristic low dielectric constant for providing a low attenuation to electric fields. The polymer can be used instead of conventional passivation layers, thereby allowing a thin, low dielectric constant layer between the object touching the physical interface, and the capacitive sensing circuits underlying the polymer.

公开(公告)号：EP1408404A3

公开(公告)日：2006-10-04

申请号：EP03255959.3

申请日：2003-09-23

Applicant: STMicroelectronics, Inc.

Inventor： Rizzo, Davide ,  Colavin, Osvaldo

IPC: G06F7/24 ,  G06F7/02

CPC classification number: G06F17/30985 ,  G06F7/026 ,  G06F7/24 ,  G06F2207/226

Abstract: A data sorting apparatus comprising 1) a storage sorter that sorts a data set according to a defined criteria; and 2) a query mechanism that receives intermediate sorted data values from the storage sorter and compares the intermediate sorted data values to at least one key value. The storage sorter comprises a priority queue for sorting the data set, wherein the priority queue comprises M processing elements. The query mechanism receives the intermediate sorted data values from the M processing elements. The query mechanism comprises a plurality of comparison circuits, each of the comparison circuits capable of detecting if one of the intermediate sorted data values is equal to the at least one key value or, if no match exists, extracting the minimal value greater than (or less than according to a defined criteria) the at least one key value.

公开(公告)号：EP1610271A3

公开(公告)日：2006-09-20

申请号：EP05253466.6

申请日：2005-06-06

Applicant: STMicroelectronics, Inc.

Inventor： Hong, Li ,  Chen, George-Qian

IPC: G06T7/00

CPC classification number: G06K9/20 ,  G06K2209/40 ,  G06T7/593

Abstract: An image matching method and system for use with multiple images of a scene captured from different angles. Image matching is performed by identifying a plurality of segments within at least two images, determining an initial disparity values for pixels in the images and then determining initial disparity planes for the segments by fitting a plane to initial disparity values for the segments. A refined disparity plane set is created by iteratively refitting the disparity planes by using various fitting cost functions and weighted linear systems. A labeling of each segment to a disparity plane is made by minimizing a global energy function that includes energy terms for segment to disparity plane matching as well as penalizing disparity plane discontinuities between adjacent image segments.

Abstract translation: 一种用于与不同角度捕获的场景的多个图像一起使用的图像匹配方法和系统。 通过识别至少两个图像内的多个片段来确定图像匹配，确定图像中的像素的初始视差值，然后通过将片段拟合到片段的初始视差值来确定片段的初始视差平面。 通过使用各种拟合成本函数和加权线性系统迭代地重新配置视差平面来创建精细视差平面集。 通过最小化包括段到视差平面匹配的能量项的全局能量函数以及惩罚相邻图像片段之间的视差平面不连续性，来将每个片段标记到视差平面进行。

公开(公告)号：EP1322060A3

公开(公告)日：2006-09-20

申请号：EP02258601.0

申请日：2002-12-13

Applicant: STMicroelectronics, Inc.

Inventor： Wang, Xianbin

IPC: H04L5/14

CPC classification number: H04L5/143 ,  H04L5/023

Abstract: To improve the performance of DSL modems, a DSL duplexing ratio for a new communication is selected according to the communications needs of an application. A required upstream and downstream bit rate for application communications is determined. From the ratio of these bit rates, a desired duplexing ratio is calculated. The operation of the modem is then adapted to choose a duplexing ratio that approximates the desired duplexing ratio for the application. To optimize modem operation, the size and position of the upstream and downstream bandwidths used for transmission are intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth provided by the chosen duplexing ratio. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated. Additionally, by intelligently selecting the position of the used bandwidth within the total available bandwidth, near-end crosstalk (NEXT) noise may be minimized.

公开(公告)号：EP1292138A3

公开(公告)日：2006-09-20

申请号：EP02255650.0

申请日：2002-08-13

Applicant: STMicroelectronics, Inc.

Inventor： Haddad, Semir S.

IPC: H04N5/783

CPC classification number: H04N5/76 ,  G11B27/005 ,  G11B27/3027 ,  G11B2220/216 ,  G11B2220/2562 ,  H04N5/783 ,  H04N5/85 ,  H04N9/8042 ,  H04N9/8063

Abstract: There is disclosed an apparatus for implementing special mode playback operations in a digital video recorder (650). The apparatus comprises an Intra frame indexing device (725) capable of receiving an incoming MPEG video stream and identifying therein data packets associated with Intra frames, wherein the Intra frame indexing device (725) modifies header information in a first data packet associated with a first Intra frame to include location information identifying a storage address of a second data packet associated with a second Intra frame.

公开(公告)号：EP1694102A1

公开(公告)日：2006-08-23

申请号：EP06250805.6

申请日：2006-02-15

Applicant: STMicroelectronics, Inc.

Inventor： Hopkins, Thomas L.

IPC: H05B41/40

CPC classification number: H05B41/40

Abstract: A fluorescent lamp assembly (100) includes a fluorescent lamp ballast (104) capable of detecting at least one of a plurality of input signals (120) and generating an output signal (110). The output signal (110) is associated with a power level that is based on the at least one detected input signal. The fluorescent lamp assembly (100) also includes a fluorescent lamp (102) capable of receiving the output signal (110) and generating light. An intensity of the light is based on the power level associated with the output signal.

Abstract translation: 一种荧光灯组件（100）包括一个荧光灯镇流器（104），其能够检测输入信号（120）中的多个至少一个，并且在输出信号（110）产生的。 的输出信号（110）与没有基于所述至少一个检测到的输入信号的功率电平相关联。 荧光灯组件（100），从而包括荧光灯（102）能够接收所述输出信号（110）并产生光的。 的光的强度是基于与所述输出信号相关联的功率电平。

公开(公告)号：EP1686460A2

公开(公告)日：2006-08-02

申请号：EP06250348.7

申请日：2006-01-23

Applicant: STMicroelectronics, Inc.

Inventor： Dash, Dillip K.

IPC: G06F9/38

CPC classification number: G06F9/325 ,  G06F9/30065 ,  G06F9/3853 ,  G06F9/3885

Abstract: A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycles for which the control signals should be generated based on that instruction. The instruction set further includes flow control instructions allowing for repetitive execution of a single instruction, repetitive execution of a block of instructions or branching within a program. Such a processor is illustrated in connection with a disk controller for a hard drive of a computer. The flexible sequencing allows a hard-drive controller to be readily reprogrammed for use in connection with different types of media or to be dynamically reprogrammed upon detection of a disk read error to increase the ability of the disk controller to recover data from a disk.

Abstract translation: 超长指令字处理器与顺序控制。 在每个循环期间，处理器基因率控制信号，以在指令的字段基于该值的功能单元。 每个指令可包括在迭代计数指定为哪个shoulderstand基于指令所产生的控制信号做循环的数目。 指令集包括流控制指令。此外，允许一个单一的指令的重复执行，指令块的重复执行或在一个程序中的分支。 这样的处理器以与用于计算机的硬盘驱动器的磁盘控制器连接示出。 柔性测序允许一个硬盘驱动器控制器能够容易地重新编程以用于与不同类型的媒体，或在检测到磁盘读取错误的被动态地重新编程，以增加磁盘控制器的从磁盘中恢复数据的能力的连接。

公开(公告)号：EP1662374A3

公开(公告)日：2006-08-02

申请号：EP06003317.2

申请日：2001-09-19

Applicant: STMicroelectronics, Inc.

Inventor： Ballachino, William Elliott

IPC: G06F7/50

CPC classification number: G06F7/507 ,  G06F7/50 ,  G06F2207/3876

Abstract: An M-bit adder (300) capable of receiving a first M-bit argument (A0-A31), a second M-bit argument (B0-B31), and a carry-in (CI) bit comprising M adder cells (C0-C31) arranged in R rows, wherein each row generates a carry-out bit that is the carry-in bit to the next higher row, wherein a least significant adder cell (C0) in a first one of said rows of adder cells receives a first data bit, A x , from said first M-bit argument and a first data bit, B x , from said second M-bit argument, and generates a first conditional carry-out bit, C x (1), and a second conditional carry-out bit, C x (0), wherein said C x (1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding said first row is a 1 and said C x (0) bit is calculated assuming said row carry-out bit from said second row is a 0, characterised in that the least significant adder cell (C0) generates a first conditional sum bit S x (1) calculated assuming said row carry-out bit from said second row is a 1, and a second conditional sum bit S x (0) assuming said row carry-out bit from said second row is a 0, and wherein each row of adder cells contains N adder cells and said preceding row of adder cells contains less than N adder cells and physically locating the least significant adder cell of each of the 2nd to the R'th rows at the end of the preceding row.

Abstract translation: 能够接收包括M个加法器单元（C0）的第一M位自变量（A0-A31），第二M位自变量（B0-B31）和进位（C1）位的M位加法器（300） 其中每行产生一个进位比特，它是进位比特到下一个更高的行，其中所述加法器单元的第一行中的最低有效加法器单元（C0）接收 来自所述第一M位自变量的第一数据位Ax和来自所述第二M位自变量的第一数据位Bx，并且生成第一条件执行位Cx（1）和第二条件进位 （0），其中假定来自所述第一行之前的第二行加法器单元的行输出位是1并且所述Cx（0）位是假定所述Cx 其特征在于最低有效加法器单元（C0）产生假设来自所述第二行的所述行输出位为1而计算的第一条件和位Sx（1） 和一秒钟 假定来自所述第二行的所述行输出位为0，并且其中每行加法器单元包含N个加法器单元，并且所述前一行加法器单元包含少于N个加法器单元并物理定位 在前一行结尾的第二行到第R行中每一行的最低有效加法单元。

公开(公告)号：EP1434145A3

公开(公告)日：2006-08-02

申请号：EP03257662.1

申请日：2003-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Huang, Lun Bin ,  Rajgopal, Suresh ,  Richardson, Nicholas Julian

IPC: G06F17/30

CPC classification number: G06F17/30985

Abstract: A series of hardware pipeline units each processing a stride during prefix search operations on a multi-bit trie includes, within at least one pipeline unit other than the last pipeline unit, a mechanism for retiring search results from the respective pipeline unit rather than passing the search results through the remaining pipeline units. Early retirement may be triggered by either the absence of subsequent strides to be processed or completion (a miss or end node match) of the search, together with an absence of active search operations in subsequent pipeline units. The early retirement mechanism may be included in those pipeline units corresponding to a last stride for a maximum prefix length shorter than the pipeline (e.g., 20 or 32 bits rather than 64 bits), in pipeline units selected on some other basis, or in every pipeline unit. Worst-case and/or average latency for prefix search operations is reduced.

公开(公告)号：EP1014380B1

公开(公告)日：2006-07-05

申请号：EP99310030.4

申请日：1999-12-13

Applicant: STMicroelectronics, Inc.

Inventor： Taylor, Ronald Thomas

IPC: G11C8/00 ,  G11C11/408

CPC classification number: G11C8/08 ,  G11C11/4085