公开(公告)号：EP1550949A2

公开(公告)日：2005-07-06

申请号：EP04257905.2

申请日：2004-12-17

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo ,  Soni, Vineet ,  Rizzo, Davide

IPC: G06F9/30

CPC classification number: G06F9/30134 ,  G06F8/4452 ,  G06F9/30032

Abstract: A system for supporting software pipelining using a shifting register queue is provided. The system includes a register file that comprises a plurality of registers. The register file is operable to receive a shift mask signal and a shift signal and to identify a shifting register queue within the register file based on the shift mask signal. The shifting register queue comprises a plurality of queue registers. The register file is further operable to shift the contents of the queue registers based on the shift signal.

Abstract translation: 本发明提供一种用于使用移位寄存器队列支持软件流水线系统。 该系统包括一个寄存器文件没有包括寄存器的多元性。 寄存器文件是可操作以接收一个移掩模信号和移位信号，并基于所述移掩模信号的寄存器文件内识别移位寄存器队列。 移位寄存器队列包括的队列寄存器复数。 寄存器文件进一步可操作以基于所述移位信号队列寄存器的内容移位。

公开(公告)号：EP1418500A2

公开(公告)日：2004-05-12

申请号：EP03256838.8

申请日：2003-10-29

Applicant: STMicroelectronics, Inc.

Inventor： Rizzo, Davide ,  Colavin, Osvaldo

IPC: G06F9/45 ,  G06F1/32

CPC classification number: G06F8/4432 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/41

Abstract: A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.

公开(公告)号：EP1710693A3

公开(公告)日：2007-11-14

申请号：EP06251747.9

申请日：2006-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Rizzo, Davide

IPC: G06F9/38

CPC classification number: G06F9/383

Abstract: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is.transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.

公开(公告)号：EP1710693A2

公开(公告)日：2006-10-11

申请号：EP06251747.9

申请日：2006-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Rizzo, Davide

IPC: G06F9/38

CPC classification number: G06F9/383

Abstract: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is.transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.

Abstract translation: 处理器执行一个或多个预取线程和一个或多个主计算线程。 每个预取线程在主计算线程之前执行指令以检索主计算线程的数据，例如主计算线程在不久的将来可能使用的数据。 针对预取线程检索数据并存储在存储器中，例如从外部存储器读取并存储在缓冲器中的数据。 预取控制器确定存储器是否已满。 如果内存已满，缓存控制器至少停止一个预取线程。 停顿可以继续，直到至少一些数据从存储器传送到高速缓存以供至少一个主计算线程使用。 然后重新激活停滞的预取线程或线程。

公开(公告)号：EP1408404A3

公开(公告)日：2006-10-04

申请号：EP03255959.3

申请日：2003-09-23

Applicant: STMicroelectronics, Inc.

Inventor： Rizzo, Davide ,  Colavin, Osvaldo

IPC: G06F7/24 ,  G06F7/02

CPC classification number: G06F17/30985 ,  G06F7/026 ,  G06F7/24 ,  G06F2207/226

Abstract: A data sorting apparatus comprising 1) a storage sorter that sorts a data set according to a defined criteria; and 2) a query mechanism that receives intermediate sorted data values from the storage sorter and compares the intermediate sorted data values to at least one key value. The storage sorter comprises a priority queue for sorting the data set, wherein the priority queue comprises M processing elements. The query mechanism receives the intermediate sorted data values from the M processing elements. The query mechanism comprises a plurality of comparison circuits, each of the comparison circuits capable of detecting if one of the intermediate sorted data values is equal to the at least one key value or, if no match exists, extracting the minimal value greater than (or less than according to a defined criteria) the at least one key value.

公开(公告)号：EP1710693B1

公开(公告)日：2011-08-03

申请号：EP06251747.9

申请日：2006-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Rizzo, Davide

IPC: G06F9/38

CPC classification number: G06F9/383

公开(公告)号：EP1550949A3

公开(公告)日：2007-10-24

申请号：EP04257905.2

申请日：2004-12-17

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo ,  Soni, Vineet ,  Rizzo, Davide

IPC: G06F9/30

CPC classification number: G06F9/30134 ,  G06F8/4452 ,  G06F9/30032

Abstract: A system for supporting software pipelining using a shifting register queue is provided. The system includes a register file that comprises a plurality of registers. The register file is operable to receive a shift mask signal and a shift signal and to identify a shifting register queue within the register file based on the shift mask signal. The shifting register queue comprises a plurality of queue registers. The register file is further operable to shift the contents of the queue registers based on the shift signal.

公开(公告)号：EP1422616A2

公开(公告)日：2004-05-26

申请号：EP03256719.0

申请日：2003-10-23

Applicant: STMicroelectronics, Inc.

Inventor： Rizzo, Davide ,  Colavin, Osvaldo

IPC: G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30072

Abstract: Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will execute only if the predicate bit of every register containing a source operand is true. The predicate bit, if any, of the destination register is set to the logical AND of the source registers' predicates. Similarly, in a non-programmable processor synthesized with predicated operand support, an operator will perform the associated function depending on the state of inputs' predicates. The output predicate is evaluated as the logical AND of the inputs' predicates. An additional bit for each data register, a change in the semantics of the instructions to include predication, and a few additional instructions to save and restore register predicate bits and to specifically set or reset a register's predicate bit are required.

Abstract translation: 指令执行的完全预测由操作数谓词提供，其中每个操作数具有直观地指示操作数值的有效性的相关联的谓词位。 在支持操作数预测的可编程处理器中，只有当包含源操作数的每个寄存器的谓词位都为真时，才执行指令。 目标寄存器的谓词位（如果有的话）被设置为源寄存器的谓词的逻辑AND。 类似地，在用预定操作数支持合成的非可编程处理器中，操作者将根据输入谓词的状态来执行相关联的功能。 输出谓词被评估为输入谓词的逻辑AND。 需要每个数据寄存器的附加位，指令的语义变化以包括预测，以及一些额外的指令来保存和恢复寄存器谓词位，并且具体设置或复位寄存器的谓词位。

公开(公告)号：EP1418500A3

公开(公告)日：2006-07-05

申请号：EP03256838.8

申请日：2003-10-29

Applicant: STMicroelectronics, Inc.

Inventor： Rizzo, Davide ,  Colavin, Osvaldo

IPC: G06F9/45 ,  G06F1/32

CPC classification number: G06F8/4432 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/41

Abstract: A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.

Abstract translation: 执行一组候选内核中的一个协处理器中的应用程序运行在满足由编译器和数据带宽的限制强加进度约束的最小时钟频率环路。 最佳时钟频率是静态确定的由编译器所开采和由软件控制的时钟电路在运行时执行。 功耗节约和最佳的资源使用率，因此通过适应于协处理器时钟速率为每个不同的内核循环实现的运行时间来实现的。

公开(公告)号：EP1422618A3

公开(公告)日：2005-12-07

申请号：EP03257332.1

申请日：2003-11-20

Applicant: STMicroelectronics, Inc.

Inventor： Rizzo, Davide ,  Colavin, Osvaldo

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3879 ,  G06F9/3891 ,  G06F15/8007 ,  G06F15/8015

Abstract: Clustered VLIW processing elements, each preferably simple and identical, are coupled by a runtime reconfigurable inter-cluster interconnect to form a coprocessor executing only those portions of a program having high instruction level parallelism. The initial portion of each program segment executed by the coprocessor reconfigures the interconnect, if necessary, or is skipped. Clusters may be directly connected to a subset of neighboring clusters, or indirectly connected to any other cluster, a hierarchy exposed to the programming model and enabling a larger number of clusters to be employed. The coprocessor is idled during remaining portions of the program to reduce power dissipation.