公开(公告)号：US20240176129A1

公开(公告)日：2024-05-30

申请号：US18193223

申请日：2023-03-30

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Sandrine VILLENAVE ,  Quentin ABADIE

IPC: G02B26/00 ,  G01J3/26 ,  G02B5/28

CPC classification number: G02B26/001 ,  G01J3/26 ,  G02B5/28

Abstract: The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, at least one resonant cavity comprising a transparent region having a first refraction index and laterally delimited by a reflective peripheral vertical wall, and at least one resonant element formed in said region.

公开(公告)号：US11984360B2

公开(公告)日：2024-05-14

申请号：US17728088

申请日：2022-04-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gregory Avenier ,  Alexis Gauthier ,  Pascal Chevalier

IPC: H01L21/82 ,  H01L21/3105 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/66 ,  H01L29/737 ,  H01L29/93

CPC classification number: H01L21/8222 ,  H01L21/31056 ,  H01L21/8249 ,  H01L27/0664 ,  H01L29/66174 ,  H01L29/66242 ,  H01L29/7371 ,  H01L29/93

Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.

公开(公告)号：US20240153557A1

公开(公告)日：2024-05-09

申请号：US18535335

申请日：2023-12-11

Applicant: Universite D'Aix Marseille ,  Centre National de la Recherche Scientifique ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Michel PORTAL ,  Vincenzo DELLA MARCA ,  Jean-Pierre WALDER ,  Julien GASQUEZ ,  Philippe BOIVIN

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0054 ,  G11C2213/72

Abstract: A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.

公开(公告)号：US11957067B2

公开(公告)日：2024-04-09

申请号：US17328917

申请日：2021-05-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H10N70/20 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/061 ,  H10N70/253 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/8828 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

公开(公告)号：US11955481B2

公开(公告)日：2024-04-09

申请号：US17992602

申请日：2022-11-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L27/08 ,  H01L21/8228 ,  H01L27/082

CPC classification number: H01L27/0826 ,  H01L21/82285

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

公开(公告)号：US20240105730A1

公开(公告)日：2024-03-28

申请号：US18532984

申请日：2023-12-07

Applicant: STMicroelectronics France ,  STMicroelectronics (Crolles 2) SAS

Inventor： Olivier WEBER ,  Christophe LECOCQ

IPC: H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/092

Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

公开(公告)号：US11901278B2

公开(公告)日：2024-02-13

申请号：US18095629

申请日：2023-01-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Pierre Carrere ,  Francois Guyader

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L31/02

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49894 ,  H01L31/02016

Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.

公开(公告)号：US20240023465A1

公开(公告)日：2024-01-18

申请号：US18186109

申请日：2023-03-17

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bruno REIG ,  Vincent PUYAL ,  Stephane MONFRAY ,  Alain FLEURY ,  Philippe CATHELIN

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/823 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/011

Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.

公开(公告)号：US11875847B2

公开(公告)日：2024-01-16

申请号：US17673550

申请日：2022-02-16

Applicant: Universite D'Aix Marseille ,  Centre National De La Recherche Scientifique ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Jean-Michel Portal ,  Vincenzo Della Marca ,  Jean-Pierre Walder ,  Julien Gasquez ,  Philippe Boivin

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0054 ,  G11C2213/72

Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.

公开(公告)号：US11837678B2

公开(公告)日：2023-12-05

申请号：US17486219

申请日：2021-09-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles Baudot ,  Sebastien Cremer ,  Nathalie Vulliet ,  Denis Pellissier-Tanon

IPC: H01L27/146 ,  H01L31/109 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/105

CPC classification number: H01L31/109 ,  H01L31/028 ,  H01L31/02327 ,  H01L31/105 ,  H01L31/1804

Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.