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    Three-dimensional polymer nano/micro molding by sacrificial layer technique
    211.
    发明申请
    Three-dimensional polymer nano/micro molding by sacrificial layer technique 审中-公开
    通过牺牲层技术的三维聚合物纳米/微型成型

    公开(公告)号：US20030087198A1

    公开(公告)日：2003-05-08

    申请号：US10246610

    申请日：2002-09-18

    Inventor： Saman Mangala Dharmatilleke ,  H. Thurman Henderson

    IPC: G03F007/00

    CPC classification number: B81C1/00119 ,  B81B2201/058 ,  B81C2201/0108

    Abstract: A procedure is presented herein for formation of NEMS/MEMS components and systems with direct arbitrary three-dimensionality for the first time in NEMS/MEMS fabrication. This method leads also to a simple and effective external nullquick-connectionnull interconnect scheme where ordinary fused silica tubes may be press-fitted into the surface opening of this system to withstand high pressure. This method may be extended for connection of multiple levels of polymer fluidic motherboards together using small sections of fused silica tubing, with no loss of stacking volume because of the lack of any connector lips or bosses. This scheme gives the flexibility of allowing multiple stacks of polymeric 3-D components (motherboards) while being able to control the channel lengths within the stacks as desired. Mixing chambers can also be molded in a single silicone elastomer (or other material) layer, because true three-dimensionality is trivially possible without the complexity of multi stacked lithography.

    Abstract translation: 本文介绍了在NEMS / MEMS制造中首次形成具有直接任意三维的NEMS / MEMS部件和系统的程序。 这种方法还引入了一种简单有效的外部“快速连接”互连方案，其中普通的熔融石英管可以压配合到该系统的表面开口中以承受高压。 这种方法可以延长，以便使用小段熔融石英管将多层聚合物流体母板连接在一起，由于没有任何连接器嘴或凸起部分而没有堆积体积的损失。 该方案给出了允许多层聚合物3-D组件（母板）同时能够根据需要控制堆叠内的通道长度的灵活性。 混合室也可以模制成单个硅酮弹性体（或其他材料）层，因为真正的三维性几乎是可能的，而不需要多层叠光刻的复杂性。

    Semiconductor device and method of manufacturing the same
    212.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20020127822A1

    公开(公告)日：2002-09-12

    申请号：US10083712

    申请日：2002-02-25

    Inventor： Katsumichi Ueyanagi ,  Mitsuo Sasaki ,  Toshiaki Sakai

    IPC: H01L021/30 ,  H01L021/46 ,  H01L027/01

    CPC classification number: B81B3/001 ,  B81C2201/0108 ,  G01P15/0802 ,  G01P15/123 ,  H01L21/31111 ,  H01L21/76251

    Abstract: A high-concentration impurity region is formed on all or a part of a surface of an Si forming the third layer, an oxide film (SiO2) forming the second layer is formed on the entire surface of the third layer, the third layer and an Si substrate forming the first layer are bonded together, and the Si forming the third layer is mirror-polished to manufacture an SOI wafer. A resist is then patterned on the SOI wafer, grooves and holes for specifying the contour of the structure are formed in the Si forming the third layer, and the oxide film SiO2 forming the second layer opposed to the formed detecting structure is removed. At the same time, an uneveness of about 0.01 to 0.5 nullm is formed on the surface of the third layer, on which the high-concentration impurity region is formed. The unevenness reduces the contact area between the third layer and the first layer, and reduces the adhering power of the third layer toward the first layer, which is generated by a surface tension 300 of liquid, to surely prevent a sticking phenomenon.

    Abstract translation: 在形成第三层的Si的表面的全部或一部分上形成高浓度杂质区，在第三层，第三层和第三层的整个表面上形成形成第二层的氧化物膜（SiO 2） 形成第一层的Si衬底接合在一起，并且形成第三层的Si被镜面抛光以制造SOI晶片。 然后在SOI晶片上图案化抗蚀剂，在形成第三层的Si中形成用于指定结构轮廓的凹槽和孔，并且去除形成与形成的检测结构相对的第二层的氧化物膜SiO 2。 同时，在形成高浓度杂质区域的第三层的表面上形成约0.01至0.5μm的不平整度。 不均匀性降低了第三层与第一层之间的接触面积，并且降低了由液体的表面张力300产生的第三层朝向第一层的粘附力，以确保防止粘附现象。

    PACKAGING COMPATIBLE WAFER LEVEL CAPPING OF MEMS DEVICES
    213.
    发明授权
    PACKAGING COMPATIBLE WAFER LEVEL CAPPING OF MEMS DEVICES 有权

    公开(公告)号：EP2788280B1

    公开(公告)日：2018-06-20

    申请号：EP12810454.4

    申请日：2012-12-06

    Applicant: Georgia Tech Research Corporation

    Inventor： KOHL, Paul, A. ,  SAHA, Rajarshi ,  FRITZ, Nathan

    IPC: B81C1/00

    CPC classification number: B81C1/00261 ,  B81B3/0018 ,  B81C1/00333 ,  B81C2201/0108 ,  B81C2203/0154

    Abstract: This invention discloses and claims a cost-effective, wafer-level package process for microelectromechanical devices (MEMS). Specifically, the movable part of MEMS device is encapsulated and protected while in wafer form so that commodity, lead-frame packaging can be used. An overcoat polymer, such as, epoxycyclohexyl polyhedral oligomeric silsesquioxanes (EPOSS) has been used as a mask material to pattern the sacrificial polymer as well as overcoat the air-cavity. The resulting air-cavities are clean, debris-free, and robust. The cavities have substantial strength to withstand molding pressures during lead-frame packaging of the MEMS devices. A wide range of cavities from 20 μm×400 μm to 300 μm×400 μm have been fabricated and shown to be mechanically stable. These could potentially house MEMS devices over a wide range of sizes. The strength of the cavities has been investigated using nano-indentation and modeled using analytical and finite element techniques. Capacitive resonators packaged using this protocol have shown clean sensing electrodes and good functionality.

    Procédé de fabrication de microcanaux sur un support et support comprenant de tels microcanaux
    217.
    发明授权
    Procédé de fabrication de microcanaux sur un support et support comprenant de tels microcanaux 有权
    Procédéde fabrication de microcanaux sur un support and support comprenant de tels microcanaux

    公开(公告)号：EP2401224B1

    公开(公告)日：2012-08-22

    申请号：EP10710083.6

    申请日：2010-02-24

    Applicant: Universite Des Sciences Et Technologies De Lille

    Inventor： ABBAS, Abdennour ,  GUILLOCHON, Didier ,  BOCQUET, Bertrand ,  SUPIOT, Philippe

    IPC: B81C1/00

    CPC classification number: B81C1/00071 ,  B81B2201/0214 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C2201/0108 ,  B81C2201/018

    Abstract: The invention relates to a method for making microchannels on a substrate, and to a substrate including such microchannels, which can particularly be used in the production of microstructured substrates for microelectronic, microfluidic and/or micromechanical systems. The method includes a step of (a) making at least one or at least two patterns (2) on the surface of a lower layer (1), and a step (b) of depositing, onto the lower layer and the pattern(s), a layer (3) of a polymer material produced by polymerisation in an optionally remote plasma-enhanced chemical vapour deposition reactor (PECVD, optionally RPECVD) of an organic or organometallic monomer with siloxane functions, e.g. tetramethyldisiloxane. The layer of polymer material is deposited so as to create, in the place of the pattern and after the decomposition of said pattern, or between two patterns without development-decomposition, a channel (4a, 4b, 4c, 4d), which is closed on at least a portion of the length thereof.

    Abstract translation: 本发明涉及一种用于在基底上制造微通道的方法，并且涉及一种包括这种微通道的基底，其特别可以用于微电子，微流体和/或微机械系统的微结构基底的生产。 该方法包括以下步骤：（a）在下层（1）的表面上制作至少一个或至少两个图案（2）;以及步骤（b），在下层和图案上 ），通过在具有硅氧烷官能团的有机或有机金属单体的任选远程等离子体增强化学气相沉积反应器（PECVD，任选RPECVD）中聚合产生的聚合物材料层（3），例如 四甲基二硅氧烷。 沉积聚合物材料层以便在图案的位置中和在所述图案分解之后或在没有显影分解的两个图案之间产生通道（4a，4b，4c，4d），所述通道（4a，4b，4c，4d） 在其至少一部分长度上。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    220.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：EP2219215A1

    公开(公告)日：2010-08-18

    申请号：EP08864653.4

    申请日：2008-12-12

    Applicant: Fujikura, Ltd.

    Inventor： YAMAMOTO, Satoshi ,  HASHIMOTO, Hirokazu

    IPC: H01L23/02 ,  H01L27/14 ,  H01L29/84 ,  B81C3/00

    CPC classification number: B81C1/00317 ,  B81C2201/0104 ,  B81C2201/0108 ,  B81C2201/0125 ,  B81C2203/0118 ,  B81C2203/0145 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing a semiconductor device includes: a bonding step of bonding a first substrate with optical transparency and a second substrate having a surface on which a functional element is provided to each other such that the functional element faces the first substrate; a thinning step of thinning at least one of the first and second substrates; and a through-hole forming step of forming a cavity and a through-hole communicated with the cavity in at least part of a bonding portion between the first and second substrates. According to the present invention, it is possible to prevent irregularities or cracks caused by the presence or absence of the cavity and more regularly thin the substrate. In addition, it is possible to manufacture a semiconductor device capable of contributing to the miniaturization of devices and electronic equipment having the devices, using a more convenient process.

    Abstract translation: 一种制造半导体器件的方法包括：键合步骤，将具有光学透明性的第一基板和具有其上设置有功能元件的表面的第二基板彼此键合，使得功能元件面向第一基板; 减薄第一和第二基板中的至少一个的减薄步骤; 以及通孔形成步骤，在第一和第二基板之间的接合部分的至少一部分中形成腔体和与腔体连通的通孔。 根据本发明，可以防止由空腔的存在或不存在引起的不规则或裂缝，并且更规则地使基板变薄。 此外，可以使用更便利的工艺来制造能够有助于装置和具有该装置的电子设备的小型化的半导体装置。

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