公开(公告)号：EP1085410A2

公开(公告)日：2001-03-21

申请号：EP00307544.7

申请日：2000-09-01

Applicant: STMicroelectronics, Ltd.

Inventor： Shann, Richard

IPC: G06F9/445

CPC classification number: G06F8/54

Abstract: An executable program is prepared from a plurality of object code modules, at least one of the object code modules including section data specifying a plurality of code sequences each associated with relocation instructions identifying condition parameters. The executable program is prepared by reading the relocation instructions and determining for each condition parameter whether or not the condition specified for that parameter is satisfied and on the basis of that determination, selecting only one of the code sequences for inclusion in the executable program.
A linker for preparing the executable program includes a stack, a relocation module for reading the relocations and carrying out the relocation operations, the relocation module being responsive to a value recalled from the stack to select one of the code sequences in dependence on the value, a section data module for holding section data which is subject to the relocation operations and a program forming a module for preparing executable programs. The linker may be controlled by a computer program in the form of one of the object code modules.
Also disclosed is a method of assembling an object code module such that the assembled object code module includes the conditional code sequences.

Abstract translation: 从多个对象代码模块准备可执行程序，至少一个目标代码模块包括指定多个代码序列的段数据，每个代码序列都与识别条件参数的重定位指令相关联。 通过读取重定位指令并确定每个条件参数来确定是否满足为该参数指定的条件并且基于该确定，仅选择用于包含在可执行程序中的代码序列之一来准备可执行程序。 用于准备可执行程序的链接器包括堆栈，用于读取重新定位并执行重定位操作的重定位模块，所述重定位模块响应于从堆栈调用的值，以根据该值选择一个代码序列， 用于保持经受重定位操作的段数据的段数据模块和形成用于准备可执行程序的模块的程序。 链接器可以由计算机程序以目标代码模块之一的形式来控制。 还公开了组装目标代码模块的方法，使得组装的目标代码模块包括条件代码序列。

公开(公告)号：EP0981080A1

公开(公告)日：2000-02-23

申请号：EP99304339.7

申请日：1999-06-03

Applicant: Stmicroelectronics, Ltd.

Inventor： Knowles, Simon

IPC: G06F7/50

CPC classification number: G06F7/508 ,  G06F2207/5063

Abstract: A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimised.

Abstract translation: 描述了一种设计加法电路的方法，以及根据该方法设计的加法电路。 优化了设计技术，以便于设计最小深度的加法电路。 设计技术考虑了加法电路的逻辑级数以及通过跨越路径连接这些级的方式来创建扇出节点。 可以优化每个级别的扇出节点数量。

公开(公告)号：EP0971503A1

公开(公告)日：2000-01-12

申请号：EP99203398.5

申请日：1991-05-22

Applicant: Stmicroelectronics, Ltd.

Inventor： Simpson, Robert J.

IPC: H04L1/00 ,  G06F13/42 ,  H04L25/02

CPC classification number: H04L1/0063 ,  H04L1/0057 ,  H04L1/0083 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/033 ,  H04L7/048

Abstract: A communication interface for interconnecting a computer with at least one other device has a link output circuit and a link input circuit. A link output on one device is connected to a link input on another device by a data line 25 and a parallel strobe line 26. Data is transmitted on the data line 25 in serial bit strings forming a succession of tokens of predetermined lengths. Signal transitions are provided on the parallel strobe line 26 where no signal transition occurs on the data line 25. Each token includes a bit indicating the length of the token and a parity bit providing a check on bits in a preceding token.

Abstract translation: 用于将计算机与至少一个其他设备互连的通信接口具有链路输出电路和链路输入电路。 一个设备上的链接输出通过数据线25和并行选通线26连接到另一个设备上的链接输入。数据在串行比特串中在数据线25上传输，形成预定长度的连续的标记。 在并行选通线26上提供信号转换，其中在数据线25上不发生信号转换。每个令牌包括指示令牌长度的位和提供对先前令牌中的位的检查的奇偶校验位。

公开(公告)号：EP0947995A2

公开(公告)日：1999-10-06

申请号：EP99302536.0

申请日：1999-03-31

Applicant: Stmicroelectronics, Ltd.

Inventor： Docker, Steven Charles

IPC: G11C29/00

CPC classification number: G11C29/50

Abstract: A method for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the method comprising the steps of: connecting the bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards the potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test the operation of the first semiconductor arrangement.

Abstract translation: 一种用于测试包括交叉耦合排列的第一和第二晶体管以形成双稳态锁存器的半导体存储器单元的方法，晶体管的漏极分别代表第一和第二节点，每个节点用于存储高电位或低电位状态，并且每个节点被连接 到相应的半导体装置，用于替换从节点泄漏的电荷和可由字线激活的相应开关装置，用于将节点耦合到相应的位线，所述方法包括以下步骤：将位线连接到 低潜力; 激活字线以将第一节点连接到第一位线以允许第一节点上的任何电势下降到第一位线上的电势; 以及监视从第一节点到第一位线的电荷流动以测试第一半导体装置的操作。

公开(公告)号：EP4293887A1

公开(公告)日：2023-12-20

申请号：EP23178867.0

申请日：2023-06-13

Applicant: STMicroelectronics Ltd

Inventor： GONTHIER, Laurent

IPC: H02M1/00 ,  H02M7/06 ,  H02M7/162 ,  H02M1/42 ,  H02M7/12 ,  H02M7/219

Abstract: La présente description concerne un circuit convertisseur (200) d'une première tension alternative (VAC) en une deuxième tension (VOUT) comprenant : un premier thyristor (T1) ; un premier circuit de commande (CMD1) du premier thyristor (T1) ; un circuit correcteur de facteur de puissance (1013) comprenant une bobine (L1) ; et un premier circuit (203) adapté à convertir une troisième tension (VINT2) en une quatrième tension continue (VCC_CMD), dans lequel la troisième tension (VINT2) correspond à la différence de potentiel entre le potentiel d'un premier noeud (N4) relié à un noeud de sortie de la bobine (L1), et un potentiel de référence (N2) ; et la quatrième tension continue (VCC_CMD) est configurée pour alimenter le premier circuit de commande (CMD1) du premier thyristor (T1), et est référencée par rapport au même potentiel de référence (N2) que la troisième tension.

公开(公告)号：EP4273583A1

公开(公告)日：2023-11-08

申请号：EP23167777.4

申请日：2023-04-13

Applicant: STMicroelectronics Ltd ,  STMicroelectronics (Shenzhen) R&D Co., Ltd.

Inventor： RIVOT, Benoit ,  WANG, Xingyu

IPC: G01S17/89 ,  G01S17/894 ,  G05D1/00 ,  G05D1/02

Abstract: A method of operating a robotic device includes: moving (402) the robotic device towards an edge of a cliff while a ToF sensor senses reflected signals having been transmitted by the ToF sensor, the reflected signals being generated by the signals transmitted by the ToF sensor being reflected off a target object back to the ToF sensor, the ToF sensor being attached to a front of the robotic device and including an array of single-photon avalanche diode, SPAD, sensors; comparing (404) a statistical distribution of the reflected signals received at a plurality of different rows of zones configured by the array of SPADs in a region of interest, ROI, of the ToF sensor and based on the comparing detecting (406) an approaching of the edge of the cliff; and in response to detecting the approaching of the edge, changing a propulsion of the robotic device before reaching the edge.

公开(公告)号：EP4088917A1

公开(公告)日：2022-11-16

申请号：EP22168447.5

申请日：2022-04-14

Applicant: STMicroelectronics Ltd

Inventor： LIN, Yu-Tsung

IPC: B29D11/00

Abstract: A method of forming a device, the method including: depositing a first photoresist layer over a substrate, forming an array of seed lenses by patterning and reflowing the first photoresist layer, a dimension of the array of seed lenses varying across the substrate, forming a second photoresist layer over the array of seed lenses, and forming a microlens array by patterning and reflowing the second photoresist layer.

公开(公告)号：EP3866463A1

公开(公告)日：2021-08-18

申请号：EP21153703.0

申请日：2021-01-27

Applicant: STMicroelectronics Ltd

Inventor： YASER, Eli ,  SHARON, Dadi

IPC: H04N9/31

Abstract: A system (30) includes a mirror controller driving fast (43) and slow (40) axis mirrors of a projector with fast (42) and slow (36) axis drive signals to reflect a collimated light beam (45) in a scan pattern across a target. The scan pattern includes trace lines which cause display of an input video stream on the target, and retrace lines which operate to return the slow axis mirror to a proper location to begin a next frame of the scan pattern. The slow axis drive signal is generated (36) to maintain a number of trace lines in each frame of the scan pattern constant across frames, but the slow axis drive signal is modified to lock (38, 35) a phase (37) and frequency (39) of the displayed video to a phase (31) and frequency (32) of the input video stream by changing a number of retrace lines in each frame of the scan pattern on a frame-by-frame basis by a non-integer number.

公开(公告)号：EP3779558A1

公开(公告)日：2021-02-17

申请号：EP20188304.8

申请日：2020-07-29

Applicant: STMicroelectronics Ltd

Inventor： YASER, Eli ,  AMOR, Guy ,  NACHMIAS, Yotam ,  SHARON, Dadi ,  NAGOLA, Sivan

IPC: G02B26/08 ,  G02B26/10

Abstract: A control circuit includes a first control circuit (14a) generating a first drive control signal (24a) from a pre-drive signal (21), which is a frequency at which an opening angle of first and second mirrors (11a,11b) is equal, for the first mirror (11a). A second control circuit (14b) generates a second drive control signal (24b) from the pre-drive signal (21) for the second mirror (11b). First and second drivers (13a,13b) generate first and second drive signals (22a,22b) for the first and second mirrors (11a,11b) from the first and second drive control signals (24a,24b). The first and second drive control signals (22a,22b) are generated so that the first and second drive signals (22a,22b) each have a same frequency as the pre-drive signal (21) but are different in amplitude from one another to cause the first and second mirrors (11a,11b) to move at a same frequency, with a same and substantially constant given opening angle as one another, and in phase with one another.

公开(公告)号：EP3745578A1

公开(公告)日：2020-12-02

申请号：EP20177512.9

申请日：2020-05-29

Applicant: STMicroelectronics Ltd

Inventor： GONTHIER, Laurent

IPC: H02M7/155 ,  H02M1/32

Abstract: La présente description concerne un procédé de commande d'un circuit comportant deux thyristors (T1, T2) en anti-série et un condensateur alternatif (Xcap) dont les deux électrodes sont respectivement reliées à deux électrodes distinctes des thyristors, comportant une étape consistant à appliquer simultanément de mêmes courants de gâchette aux deux thyristors lorsque le circuit détecte une absence de tension alternative (Vac) aux bornes du condensateurs alternatif.