公开(公告)号：WO1997027628A1

公开(公告)日：1997-07-31

申请号：PCT/US1996017408

申请日：1996-11-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LIU, Yowjuang, W. ,  QUIAN, Feng ,  LAI, Tze-Kwai, Kelvin

IPC: H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76281 ,  H01L21/823878 ,  H01L27/0921

Abstract: A semiconductor device having the advantages of an SOI structure without the attendant disadvantages is obtained by implanting oxygen ions using the gate electrode (4) as a mask, and heating to form thin, self-aligned buried oxide regions (20, 21) extending from a field oxide region (3) under source/drain regions self-aligned with the side surfaces (4A, 4B) of the gate electrode. In other embodiments, the thin buried oxide layer extends from a point in close proximity to the field oxide region and/or partially under the gate electrode.

Abstract translation: 具有SOI结构而不伴随缺点的优点的半导体器件是通过使用栅电极（4）作为掩模注入氧离子，并加热形成薄的自对准埋氧层（20,21），其从 在与栅电极的侧表面（4A，4B）自对准的源极/漏极区之下的场氧化物区域（3）。 在其他实施例中，薄的掩埋氧化物层从靠近场氧化物区域的点和/或部分地在栅电极下方延伸。

公开(公告)号：WO1997025669A1

公开(公告)日：1997-07-17

申请号：PCT/US1996019588

申请日：1996-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  IRETON, Mark, A.

IPC: G06F09/318

CPC classification number: G06F9/382 ,  G06F9/30174 ,  G06F9/3808 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3885

Abstract: An instruction translation unit is provided which reduces instructions from a source instruction set to a set of intermediate, atomic operations. The atomic operations are then recombined into instructions in the target instruction set. An execution core coupled to the instruction translation unit may be configured to execute instructions from the target instruction set. However, compatibility with the source instruction set is maintained. By reducing a plurality of source instructions into atomic operations, portions of multiple source instructions may be combined into target instructions. The execution core may thereby be more efficiently utilized.

Abstract translation: 提供了一种指令翻译单元，其将源指令集的指令减少到一组中间原子操作。 然后将原子操作重组为目标指令集中的指令。 耦合到指令转换单元的执行核心可以被配置为执行来自目标指令集的指令。 但是，保持与源指令集的兼容性。 通过将多个源指令减少为原子操作，多个源指令的部分可以组合成目标指令。 从而可以更有效地利用执行核心。

公开(公告)号：WO1997023043A1

公开(公告)日：1997-06-26

申请号：PCT/US1996012528

申请日：1996-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SHARPE-GEISLER, Bradley, A.

IPC: H03K05/135

CPC classification number: H03K5/135

Abstract: A clock generator circuit for providing a clock signal to a dual-edged D-type flip-flop, enabling the flip-flop to be dual-edged, single-edged, or to enable a user to provide clock edge selection, asynchronous clocking, clock enabling, or a mixture of different type of clock signals. The clock generator circuit includes inputs receiving first and second enable signals and a clock signal. The clock generator circuit further includes circuitry to provide an output clock signal which transitions when a rising edge of a pulse of the clock signal is received when the first clock signal is enabled, or if a falling edge of a pulse of the clock signal is received when the second clock signal is enabled.

Abstract translation: 一种用于向双边D型触发器提供时钟信号的时钟发生器电路，使触发器能够被双边形，单边形化，或使得用户能够提供时钟沿选择，异步时钟， 时钟使能或不同类型的时钟信号的混合。 时钟发生器电路包括接收第一和第二使能信号和时钟信号的输入。 时钟发生器电路还包括提供输出时钟信号的电路，当在第一时钟信号被使能时接收到时钟信号的脉冲的上升沿时，或者如果接收到时钟信号的脉冲的下降沿 当第二个时钟信号被使能时。

公开(公告)号：WO1997022148A1

公开(公告)日：1997-06-19

申请号：PCT/US1996014943

申请日：1996-09-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHANG, Kuang-Yeh ,  LIU, Yowjuang, W.

IPC: H01L27/11

CPC classification number: H01L27/11 ,  H01L27/1112

Abstract: A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.

Abstract translation: 金属氧化物半导体静态随机存取存储器（SRAM）包括NMOS晶体管和不具有多个多晶硅层的电阻结构。 根据第一实施例，SRAM单元包括多个适当互连的NMOS晶体管，其具有由多晶硅层形成的晶体管栅极和由相同多晶硅层形成的电阻器。 根据第二实施例，SRAM单元包括多个适当互连的NMOS晶体管，覆盖NMOS晶体管的电介质层，以及穿过介电层的多晶硅电阻器，以将NMOS晶体管连接到第一金属层。 沉积在NMOS晶体管上的电介质层限定了暴露在NMOS晶体管中的漏极区域的孔。 在电介质层上沉积多晶硅层以填充孔，并且去除多余的多晶硅。

公开(公告)号：WO1997021226A1

公开(公告)日：1997-06-12

申请号：PCT/US1996012896

申请日：1996-08-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHUNG, Michael ,  YU, James

IPC: G11C16/06

CPC classification number: G05F3/262 ,  G11C5/147 ,  G11C16/30

Abstract: A system and method for providing a constant electric field that is insensitive to fluctuations in the power supply to a FLASH EPROM during erasure. The system comprises a plurality of sector source drivers and a power supply insensitive constant current source. Each sector has at least one binary storage element. Each storage element has a source. The sector source drivers couple the at least one source of a sector to be erased to the power supply insensitive constant current source. The power supply insensitive constant current source provides an electric field across the tunneling oxide which is constant and insensitive to fluctuations in the power supply. This improves the wear characteristics and lifetime of the binary storage elements. In addition, this system remedies problems associated with short channel effects, electron trapping, and the use of various voltage sources.

Abstract translation: 一种在擦除期间提供对FLASH EPROM的电源波动不敏感的恒定电场的系统和方法。 该系统包括多个扇区源驱动器和电源不敏感恒流源。 每个扇区具有至少一个二进制存储元件。 每个存储元素都有一个源。 扇区源驱动器将要擦除的扇区的至少一个源耦合到电源不敏感的恒流源。 电源不敏感恒流源提供贯穿隧道氧化物的电场，该电场对电源的波动是恒定的和不敏感的。 这改善了二进制存储元件的磨损特性和寿命。 此外，该系统解决了与短通道效应，电子捕获和各种电压源的使用相关的问题。

公开(公告)号：WO1997017762A1

公开(公告)日：1997-05-15

申请号：PCT/US1996011873

申请日：1996-07-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  REENTS, Daniel, B. ,  QUIMBY, Michael, S. ,  WAKELAND, Carl, K.

IPC: H03K19/00

CPC classification number: H03K19/0016

Abstract: Within an integrated circuit, an input/output driver circuit is provided. The input/output driver circuit is configured to provide electrical isolation and power savings when the integrated circuit is configured into a computer system such as a personal information device. By providing a mechanism permitting removal of power from the driver circuit, the integrated circuit inhibits current flow from the integrated circuit into a powdered-down peripheral device. A force term is activated, when electrical isolation is desired, to inhibit current flow into or from the integrated circuit via an input/output pad voltage level. A power savings is enabled by allowing the power down of peripheral devices coupled to the integrated circuit without the need for external buffer circuits.

Abstract translation: 在集成电路中，提供输入/输出驱动器电路。 输入/输出驱动器电路被配置为当集成电路被配置到诸如个人信息设备的计算机系统中时提供电隔离和功率节省。 通过提供允许从驱动器电路移除电力的机构，集成电路抑制从集成电路到粉末状的外围设备的电流流动。 当需要进行电气隔离时，强制项被激活，以阻止通过输入/输出焊盘电压电平流入或流出集成电路的电流。 通过允许连接到集成电路的外围设备断电而不需要外部缓冲电路，可实现省电。

公开(公告)号：WO1997017705A1

公开(公告)日：1997-05-15

申请号：PCT/US1996016460

申请日：1996-10-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  AGRAWAL, Ram ,  SPAK, Michael

IPC: G11C07/00

CPC classification number: G11C7/1006

Abstract: An x-y RAM array with a reconfigurable bit width is provided. The array contains a RAM cell columns organized into a number of column groups where the number of groups determines the bit width of the memory. The number of columns in each group are configurable thereby configuring the number of groups and thus the bit width of the memory. Multiplexor logic selects a column from each group to be accessed and passgate logic determines how the multiplexor logic is combined and thus determines the column group configuration. Decode logic provides the appropriate select signals to the multiplexor logic for selecting from the configured number of columns in each group.

Abstract translation: 提供了具有可重新配置位宽的x-y RAM阵列。 阵列包含组织成多个列组的RAM单元格列，其中组的数量确定存储器的位宽。 每个组中的列数可以配置，从而配置组的数量，从而配置存储器的位宽。 多路复用器逻辑从要访问的每个组中选择一列，而门控逻辑决定多路复用器逻辑如何组合，从而确定列组配置。 解码逻辑为多路复用器逻辑提供了适当的选择信号，用于从每组中配​​置的列数中进行选择。

公开(公告)号：WO1997016852A1

公开(公告)日：1997-05-09

申请号：PCT/US1996014316

申请日：1996-09-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LIU, David, K., Y. ,  KUAN, Ming, Sang ,  CHANG, Chi

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  Y10S438/982

Abstract: A method for reducing encroachment of an impurity implant into a channel region in a non-ESD transistor in a semiconductor circuit, the non-ESD transistor receiving both first and second implant dopants, and the circuit including a plurality of ESD transistors includes forming the ESD transistors of the circuit at a predetermined angular offset from the non-ESD transistor, and performing the second dopant implant at a predetermined tilt implant angle, wherein the non-ESD transistor has reduced encroachment of the impurity implant. A plurality of transistors formed on a semiconductor wafer include a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors. Further, the plurality of ESD transistors include the spacer regions and impurity implant regions encroaching the spacer regions further than the impurity implant regions of the non-ESD transistors.

Abstract translation: 一种用于将杂质注入减少到半导体电路中的非ESD晶体管中的沟道区域的方法，所述非ESD晶体管接收第一和第二注入掺杂剂，并且包括多个ESD晶体管的电路包括形成ESD 晶体管，其以非ESD晶体管的预定角度偏移，并以预定的倾斜注入角执行第二掺杂剂注入，其中非ESD晶体管具有减少的杂质注入侵入。 形成在半导体晶片上的多个晶体管包括多个非ESD晶体管，所述多个非ESD晶体管包括间隔区域和侵入间隔区域的杂质注入区域，以及多个ESD晶体管，所述多个ESD晶体管形成 在非ESD晶体管的预定角度偏移处。 此外，多个ESD晶体管包括比非ESD晶体管的杂质注入区域更远的间隔区域和杂质注入区域。

公开(公告)号：WO1997013202A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015416

申请日：1996-10-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FAVOR, John, G. ,  WEBER, Frederick, D.

IPC: G06F09/46

CPC classification number: G06F7/74 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/445 ,  G06F9/45533 ,  G06F9/4812

Abstract: A system management mode (SMM) (900) of operating a processor (120) includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is "soft" and freely defined. A system management interrupt (SMI) pin (960) is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.

Abstract translation: 操作处理器（120）的系统管理模式（SMM）900仅包括用于支持SMM的处理器中的一组基本硬连线钩或机构。 大多数SMM功能，例如在进入和退出SMM时执行的处理动作是“软”并自由定义的。 系统管理中断（SMI）引脚（960）连接到处理器，使得SMI引脚上的信号使处理器进入SMM模式。 SMM对所有其他处理器操作软件是完全透明的。 SMM处理程序代码和数据存储在被正常软件访问保护和隐藏的内存中。

公开(公告)号：WO1997013199A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015741

申请日：1996-10-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FAVOR, John, G. ,  BEN-MEIR, Amos

IPC: G06F09/38

CPC classification number: G06F9/382 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/3812 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857

Abstract: A superscalar microprocessor (200) includes a scheduler (280) which stores information related to operations and issues operations for out-of-order execution by execution units (251 to 257). Operations are issued without regard for the availability of operands required for execution. After the issue stage, an operand forward stage identifies operand sources which may be a register file (290) or an operation in the scheduler (280). The scheduler (280) forwards a value and state information for the operand. The state information indicates whether an operation providing the operand was or is being completed so that execution can continue. The state information can also indicate a wait until a source operation is completed. If the wait is too long, the issued operation is bumped so that another operation can be issued and executed. This reduces hold ups and increases utilization of execution units (251 to 257).

Abstract translation: 超标量微处理器（200）包括调度器（280），其存储与执行单元（251至257）的无序执行的操作和发出操作有关的信息。 发出操作，而不考虑执行所需的操作数的可用性。 在发布阶段之后，操作数转发阶段识别可以是寄存器文件（290）或调度程序（280）中的操作的操作数源。 调度器（280）转发操作数的值和状态信息。 状态信息指示提供操作数的操作是或正在完成，以便执行可以继续。 状态信息还可以指示等待，直到源操作完成。 如果等待时间太长，则发出的操作被碰撞，从而可以发出和执行另一个操作。 这减少了执行单位的持有和增加利用率（251到257）。