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公开(公告)号：US12143764B2
公开(公告)日：2024-11-12
申请号：US17686322
申请日：2022-03-03
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Federico Rizzardini , Lorenzo Bracco , Andrea Labombarda , Mauro Bardone , Stefano Paolo Rivolta , Federico Iaccarino
Abstract: The present disclosure is directed to input detection for electronic devices using electrostatic charge sensors. The devices and methods disclosed herein utilize electrostatic charge sensors to detect various touch gestures, such as long and short touches, single/double/triple taps, and swipes; and perform in-ear detection.
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公开(公告)号：US12142552B2
公开(公告)日：2024-11-12
申请号：US18070051
申请日：2022-11-28
Applicant: STMicroelectronics S.r.l.
Inventor： Fulvio Vittorio Fontana
IPC: H01L23/495 , H01L23/00 , H01L23/31 , H01L21/56
Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.
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公开(公告)号：US20240371738A1
公开(公告)日：2024-11-07
申请号：US18774478
申请日：2024-07-16
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto TIZIANI
IPC: H01L23/498 , H01L23/00 , H01L23/15 , H01L23/31 , H01L23/488 , H01L23/495 , H01L23/522 , H01L23/538
Abstract: A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.
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公开(公告)号：US12135668B2
公开(公告)日：2024-11-05
申请号：US18056012
申请日：2022-11-16
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Castellano , Francesco Bruni , Luca Gandolfi , Marco Leo
Abstract: A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.
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公开(公告)号：US12135572B2
公开(公告)日：2024-11-05
申请号：US17694182
申请日：2022-03-14
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto Cattani , Alessandro Gasparini , Stefano Ramorini
IPC: G05F1/56
Abstract: In an embodiment, a method includes: providing a voltage setpoint to a voltage converter; generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint; when the voltage setpoint is transitioning from a first voltage setpoint to a second voltage setpoint that has a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, where the output transistor includes a source terminal coupled to a first terminal of a first resistor, and where a current path of the output transistor is coupled to the voltage rail; and turning off the output transistor after the output voltage reaches the target output voltage corresponding to the second voltage setpoint.
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Patent Agency Ranking
公开(公告)号：US12134556B2
公开(公告)日：2024-11-05
申请号：US17534286
申请日：2021-11-23
Inventor： Enri Duqi , Lorenzo Baldo , Paolo Ferrari , Benedetto Vigna , Flavio Francesco Villa , Laura Maria Castoldi , Ilaria Gelmi
IPC: B81B7/00
Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.
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公开(公告)号：US12130360B2
公开(公告)日：2024-10-29
申请号：US18178110
申请日：2023-03-03
Applicant: STMicroelectronics S.r.l.
Inventor： Antonio Davide Leone , Vanni Poletto
CPC classification number: G01S15/931 , G01S7/521 , G01S7/524 , G01S2007/52007 , G01S2015/937 , H04R17/00
Abstract: In accordance with an embodiment, an ultrasound transmitter device includes a transformer comprising a secondary winding configured to be coupled to a piezoelectric transducer; a plurality of transistors coupled to the primary winding of the transformer and to a ground terminal via a sense resistor; an amplifier having an output coupled to control nodes of the plurality of transistors, a first input coupled to the sense resistor, and second input coupled to a reference resistor; a switching circuit configured to alternately couple control nodes of the plurality of transistors to an output of amplifier and to a reference node via complementary pulse signals, wherein the switching circuit is configured to turn on and turn off the plurality of transistors and operate the plurality of transistors in a push-pull manner; and a digital-to-analog converter having an output coupled to the reference resistor.
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228.发明授权公开(公告)号：US12125803B2
公开(公告)日：2024-10-22
申请号：US18121145
申请日：2023-03-14
Applicant: STMicroelectronics S.r.l.
Inventor： Paolo Crema
IPC: H01L23/495 , B23K26/0622 , B23K26/354 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , B23K103/08
CPC classification number: H01L23/562 , B23K26/0622 , B23K26/354 , H01L21/4825 , H01L21/565 , H01L23/3114 , H01L23/49503 , H01L23/49513 , H01L23/49582 , B23K2103/08
Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
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公开(公告)号：US12124713B2
公开(公告)日：2024-10-22
申请号：US18057390
申请日：2022-11-21
Inventor： Francesco Bombaci , Andrea Tosoni
IPC: G06F3/06
CPC classification number: G06F3/0629 , G06F3/0622 , G06F3/0665 , G06F3/0679
Abstract: A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.
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230.发明授权公开(公告)号：US12119746B2
公开(公告)日：2024-10-15
申请号：US17807466
申请日：2022-06-17
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Borghese , Mattia Carrera
CPC classification number: H02M3/158 , H02M1/0016 , H02M1/0022 , H02M1/0025
Abstract: In an embodiment a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, and a pulse-width modulated (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal.
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