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    External storage system with redundant storage controllers
    221.
    发明公开
    External storage system with redundant storage controllers 失效
    具有冗余存储控制器的外部存储系统

    公开(公告)号：EP0747822A2

    公开(公告)日：1996-12-11

    申请号：EP96109061.0

    申请日：1996-06-05

    Applicant: HITACHI, LTD.

    Inventor： Matsumoto, Yoshiko ,  Muraoka, Kenji

    IPC: G06F11/20

    CPC classification number: G06F11/2092 ,  G06F3/0601 ,  G06F11/1008 ,  G06F11/3433 ,  G06F2003/0697 ,  G06F2201/85

    Abstract: An external storage system has a storage unit (500) for storing data and a plurality of storage controllers (200, 400) for controlling data transfer between an upper level system (100) and the storage unit. Each storage controller has a data buffer (240, 440) for temporarily storing data and a controller (250, 450) for controlling the operation of the storage controller. The external storage system has a management memory (310) for storing management information of the plurality of storage controllers each of which accesses this memory to monitor the operation states of other storage controllers. The external storage system has a first storage controller for processing an input-output request from the upper level system and a second storage controller for standing by for backup for a failed storage controller. In accordance with load distribution information stored in the management memory, the process to be executed by the first storage controller is partially executed by the second storage controller to improve the performance of the whole external storage system.

    High-performance computer system with fault-tolerant capability
    222.
    发明公开
    High-performance computer system with fault-tolerant capability 失效
    Hochleistungsrechnersystem mit fehlertoleranterFähigkeit。

    公开(公告)号：EP0447577A1

    公开(公告)日：1991-09-25

    申请号：EP90105102.9

    申请日：1990-03-19

    Applicant: TANDEM COMPUTERS INCORPORATED

    Inventor： Cutts, Richard W. Jr. ,  Banton, Randall G. ,  Jewett, Douglas E. ,  Norwood, Peter C. ,  Debacker, Kenneth C. ,  Mehta, Nikhil A. ,  Allison, John David ,  Horst, Robert W.

    IPC: G06F11/18

    CPC classification number: G06F9/3863 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/18 ,  G06F11/181 ,  G06F11/182 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2015 ,  G06F11/2017 ,  G06F2201/85 ,  G11C29/74

    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

    Abstract translation: 容错配置中的计算机系统使用执行相同指令流的多个相同的CPU，在存储相同数据的副本的CPU的地址空间中具有多个相同的存储器模块。 多个CPU松动地同步，如通过检测诸如存储器引用的事件，并使其他任何CPU停止，直到所有执行功能同时执行; 中断可以通过确保所有CPU在其指令流中的相同点实现中断来同步。 通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。 使用两个相同的I / O总线实现I / O功能，每个总线单独地仅耦合到一个存储器模块。 许多I / O处理器耦合到两个I / O总线。 I / O设备通过一对相同（冗余）I / O处理器访问，但只有一个被指定为主动控制给定的设备; 然而，在一个I / O处理器发生故障的情况下，I / O设备可以被另一个I / O设备访问，而不需要系统关闭，即仅在指令控制下重新指定I / O设备的寄存器的地址。

    Memory management in high-performance fault-tolerant computer system
    223.
    发明公开
    Memory management in high-performance fault-tolerant computer system 失效
    说话者在fehlertolerantem Hochleistungsrechnersystem。

    公开(公告)号：EP0372578A2

    公开(公告)日：1990-06-13

    申请号：EP89122707.6

    申请日：1989-12-08

    Applicant: TANDEM COMPUTERS INCORPORATED

    Inventor： Cutts, Richard W., Jr. ,  Peet, Charles E., Jr. ,  Jewett, Douglas E. ,  Debacker, Kenneth C. ,  Mehta, Nikhil A. ,  Allison, John David ,  Horst, Robert W.

    IPC: G06F11/16 ,  G06F11/18

    CPC classification number: G06F9/3863 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/18 ,  G06F11/181 ,  G06F11/182 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2015 ,  G06F11/2017 ,  G06F2201/85 ,  G11C29/74

    Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are imple­mented using two identical I/O busses, each of which is separate­ly coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. Each CPU has its own fast cache and also local memory not accessible by the other CPUs. A hierarchical virtual memory management arrangement for this system employs demand paging to keep the most-used data in the local memory, page-swapping with the global memory. Page swapping with disk memory is through the global memory; the global memory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory. The operating system kernel is kept in local memory. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.

    Abstract translation: 容错配置的计算机系统使用三个相同的CPU执行相同的指令流，两个相同的自检存储器模块存储相同数据的重复。 三个CPU的存储器引用由连接到两个存储器模块中的每一个的三个单独端口的三个单独的总线进行。 三个CPU松动地同步，如通过检测诸如内存引用的事件，并阻止其他CPU之前的事件，直到所有执行该功能的同时; 可以通过确保所有三个CPU在其指令流中的相同点实现中断来同步中断。 通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。 使用两个相同的I / O总线实现I / O功能，每个总线单独地仅耦合到一个存储器模块。 许多I / O处理器耦合到两个I / O总线。 每个CPU都有自己的快速缓存，而且其他CPU也无法访问本地内存。 用于该系统的分层虚拟存储器管理装置采用需求寻呼来将最常用的数据保存在本地存储器中，与全局存储器进行页面交换。 与磁盘存储器进行页面交换是通过全局内存; 全局内存用作磁盘缓冲区，也可以保存可能需要加载到本地内存的页面。 操作系统内核保存在本地内存中。 存储器模块中的共享存储空间中包含一个专用写入区域，以允许诸如软件对CPU特有的状态信息进行投票。 所有CPU将状态信息写入其专用写入区域，然后所有CPU都会读取所有私有写入区域，以检测中断原因等异常的功能。

    SYSTEMS AND METHODS FOR FAULT TOLERANT COMMUNICATIONS
    224.
    发明授权
    SYSTEMS AND METHODS FOR FAULT TOLERANT COMMUNICATIONS 有权

    公开(公告)号：EP3129903B1

    公开(公告)日：2018-11-28

    申请号：EP15814364.4

    申请日：2015-06-23

    Applicant: SAS Institute Inc.

    Inventor： KNIGHT, Richard

    IPC: G06F11/20

    CPC classification number: G06F11/203 ,  G06F11/2023 ,  G06F11/2025 ,  G06F11/2028 ,  G06F11/2033 ,  G06F11/2035 ,  G06F11/2038 ,  G06F11/2041 ,  G06F11/2097 ,  G06F2201/84 ,  G06F2201/85

    Abstract: Apparatuses, systems and methods are disclosed for tolerating fault in a communications grid. Specifically, various techniques and systems are provided for detecting a fault or failure by a node in a network of computer nodes in a communications grid, adjusting the grid to avoid grid failure, and taking action based on the failure. In an example, a system may include receiving grid status information at a backup control node, the grid status information including a project status, storing the grid status information within the backup control node, receiving a failure communication including an indication that a primary control node has failed, designating the backup control node as a new primary control node, receiving updated grid status information based on the indication that the primary control node has failed, and transmitting a set of instructions based on the updated grid status information.

    STORING DATA IN A DISTRIBUTED STORAGE SYSTEM
    225.
    发明公开
    STORING DATA IN A DISTRIBUTED STORAGE SYSTEM 审中-公开

    公开(公告)号：EP3396552A2

    公开(公告)日：2018-10-31

    申请号：EP18163060.9

    申请日：2018-03-21

    Applicant: Hewlett Packard Enterprise Development L.P.

    Inventor： Vishnumolakala, Murali Krishna ,  Maheshwari, Umesh

    IPC: G06F11/10

    CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F11/2094 ,  G06F2201/85

    Abstract: According to examples, a storage node may include storage devices and a controller that may determine whether all of a plurality of data chunks of a first intra-node portion of a stripe have been stored on the storage node. Based on a determination that all of the data chunks have been stored, a first intra-node parity chunk may be stored at a second one of the storage devices, in which the first intra-node parity chunk may be determined from at least one of the data chunks of the first intra-node portion. Based on a determination that at least one of the data chunks has not been stored, storage of a first intra-node parity chunk of the stripe on the storage node may be delayed until a determination is made that all of the data chunks of the first intra-node portion have been stored at the storage node.

    ELASTIC VIRTUAL MULTIPATH RESOURCE ACCESS USING SEQUESTERED PARTITIONS
    229.
    发明公开
    ELASTIC VIRTUAL MULTIPATH RESOURCE ACCESS USING SEQUESTERED PARTITIONS 审中-公开

    公开(公告)号：EP3084617A4

    公开(公告)日：2018-01-10

    申请号：EP13899511

    申请日：2013-12-19

    Applicant: INTEL CORP

    Inventor： DOSHI KSHITIJ A ,  LE MINH TUNG DUY ,  KHANNA RAHUL ,  DORMITZER PAUL H

    IPC: G06F11/20

    CPC classification number: G06F11/1471 ,  G06F11/2033 ,  G06F11/2035 ,  G06F11/2043 ,  G06F2201/805 ,  G06F2201/85

    Abstract: Technologies for virtual multipath access include a computing device configured to sequester a recovery partition from a host partition while allowing the recovery partition to access one or more resources of the host partition such as host memory or data storage. A remote computing device determines whether the host partition is responsive. The recovery partition receives a request for host state data of the host partition from the remote computing device in response to a determination that the host partition is not responsive. The recovery partition retrieves the requested host state data using a host state index maintained by the host partition and transmits the requested host state data to the remote computing device. The host state index may identify the location of the requested host state data. The remote computing device may perform a recovery operation based on the received host state data. Other embodiments are described and claimed.

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