公开(公告)号：US11079955B2

公开(公告)日：2021-08-03

申请号：US16221832

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mustafa Hajeer ,  Thomas Willhalm ,  Amin Firoozshahian ,  Chandan Egbert

IPC: G06F3/06

Abstract: Examples relate to an approximative memory deduplication method, a controller apparatus or controller device for a memory or storage controller, a memory or storage controller, a computer system and to a computer program. The approximative memory deduplication method comprises determining a hash value of a data block. The hash value is based on a user-defined approximative hashing function. The approximative memory deduplication method comprises storing a quantized version of the data block based on the hash value using a memory or storage device of the computer system.

公开(公告)号：US11055256B2

公开(公告)日：2021-07-06

申请号：US16373339

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mustafa Hajeer

IPC: G06F15/16 ,  G06F15/173 ,  H04L29/08 ,  H04L29/06 ,  G06F15/167

Abstract: An apparatus is described. The apparatus includes logic circuitry embedded in at least one of a memory controller, network interface and peripheral control hub to process a function as a service (FaaS) function call embedded in a request. The request is formatted according to a protocol. The protocol allows a remote computing system to access a memory that is coupled to the memory controller without invoking processing cores of a local computing system that the memory controller is a component of.

公开(公告)号：US20210117334A1

公开(公告)日：2021-04-22

申请号：US17132431

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mark A. Schmisseur

IPC: G06F12/0882 ,  G06F12/0831 ,  G06F12/02 ,  G06F13/16 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide for a memory controller to manage quality of service enforcement and migration between local and pooled memory. For example, a memory controller may include logic to communicate with a local memory and with a pooled memory controller to track memory page usage on a per application basis, instruct the pooled memory controller to perform a quality of service enforcement in response to a determination that an application is latency bound or bandwidth bound, wherein the determination that the application is latency bound or bandwidth bound is based on a cycles per instruction determination, and instruct a Direct Memory Access engine to perform a migration from a remote memory to the local memory in response to a determination that the quality of service cannot be enforced.

公开(公告)号：US20210110310A1

公开(公告)日：2021-04-15

申请号：US17131462

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned M. Smith ,  Karthik Kumar ,  Sunil Cheruvu ,  Timothy Verrall

IPC: G06N20/00 ,  G06F16/27 ,  H04L29/06

Abstract: Methods and apparatus to verify trained models in edge environments are disclosed. An example apparatus to validate a trained model in an edge environment includes an attestation verifier to determine an attestation score of the model received at a first appliance, the attestation score calculated at a second appliance different from the first appliance, a comparator to compare the attestation score to a threshold, a validator to validate the model based on the comparison, and an executor to at least one of execute or deploy the model based on the validation.

公开(公告)号：US10977036B2

公开(公告)日：2021-04-13

申请号：US16336884

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Patrick Lu ,  Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Martin P. Dimitrov

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/0862 ,  G06F9/38

Abstract: An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.

公开(公告)号：US10922265B2

公开(公告)日：2021-02-16

申请号：US15634128

申请日：2017-06-27

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Nicolae Popovici ,  Thomas Willhalm

IPC: G06F12/00 ,  G06F15/173 ,  G06F12/0831 ,  G06F9/52 ,  G06F12/0813 ,  G06F12/084 ,  G06F9/46

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a transaction request to perform a transaction with the memory, the transaction request including a synchronization indication to indicate utilization of transaction synchronization to perform the transaction. Embodiments may include sending a request to a caching agent to perform the transaction, receiving a response from the caching agent, the response to indicate whether the transaction conflicts or does not conflict with another transaction, and performing the transaction if the response indicates the transaction does not conflict with the other transaction, or delaying the transaction for a period of time if the response indicates the transaction does conflict with the other transaction.

公开(公告)号：US20200226272A1

公开(公告)日：2020-07-16

申请号：US16830703

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mark Schmisseur ,  Thomas Willhalm

IPC: G06F21/60 ,  G06F3/06 ,  H04W12/00

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to process memory operation requests from a memory controller, and provide a front end interface to remote pooled memory hosted at a near edge device. An embodiment of another electronic apparatus may include local memory and logic communicatively coupled the local memory, the logic to allocate a range of the local memory as remote pooled memory, and provide a back end interface to the remote pooled memory for memory requests from a far edge device. Other embodiments are disclosed and claimed.

公开(公告)号：US10599579B2

公开(公告)日：2020-03-24

申请号：US16017872

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Francesc Guim Bernat ,  Benjamin Graniello ,  Thomas Willhalm ,  Mustafa Hajeer

IPC: G06F12/00 ,  G06F12/0895 ,  G06F12/0846 ,  G06F12/0862

Abstract: Cache on a persistent memory module is dynamically allocated as a prefetch cache or a write back cache to prioritize read and write operations to a persistent memory on the persistent memory module based on monitoring read/write accesses and/or user-selected allocation.

公开(公告)号：US20200076682A1

公开(公告)日：2020-03-05

申请号：US16367626

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Benjamin Graniello ,  Timothy Verrall ,  Andrew J. Herdrich ,  Rashmin Patel ,  Monica Kenguva ,  Brinda Ganesh ,  Alexander Vul ,  Ned M. Smith ,  Suraj Prabhakaran

IPC: H04L12/24

Abstract: Technologies for providing multi-tenant support in edge resources using edge channels include a device that includes circuitry to obtain a message associated with a service provided at the edge of a network. Additionally, the circuitry is to identify an edge channel based on metadata associated with the message. The edge channel has a predefined amount of resource capacity allocated to the edge channel to process the message. Further, the circuitry is to determine the predefined amount of resource capacity allocated to the edge channel and process the message using the allocated resource capacity for the identified edge channel.

公开(公告)号：US10541942B2

公开(公告)日：2020-01-21

申请号：US15941943

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Anil Rao ,  Suraj Prabhakaran ,  Mohan Kumar ,  Karthik Kumar

IPC: H04L12/947 ,  H04L12/66 ,  H04L12/801 ,  H04L12/931

Abstract: Technologies for accelerating edge device workloads at a device edge network include a network computing device which includes a processor platform that includes at least one processor which supports a plurality of non-accelerated function-as-a-service (FaaS) operations and an accelerated platform that includes at least one accelerator which supports a plurality of accelerated FaaS (AFaaS) operation. The network computing device is configured to receive a request to perform a FaaS operation, determine whether the received request indicates that an AFaaS operation is to be performed on the received request, and identify compute requirements for the AFaaS operation to be performed. The network computing device is further configured to select an accelerator platform to perform the identified AFaaS operation and forward the received request to the selected accelerator platform to perform the identified AFaaS operation. Other embodiments are described and claimed.