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    DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER
    243.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER 审中-公开
    动态地址翻译与翻译例外的合格者

    公开(公告)号：WO2009106457A1

    公开(公告)日：2009-09-03

    申请号：PCT/EP2009/051864

    申请日：2009-02-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GREINER, Dan ,  HELLER, Lisa ,  OSISEK, Damian ,  PFEFFER, Erwin

    Inventor： GREINER, Dan ,  HELLER, Lisa ,  OSISEK, Damian ,  PFEFFER, Erwin

    IPC: G06F12/10

    CPC classification number: G06F12/0284 ,  G06F3/0604 ,  G06F3/0667 ,  G06F3/067 ,  G06F9/455 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/657

    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

    Abstract translation: 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的动态地址转换进行。 响应于在动态地址转换期间发生的翻译中断，比特被存储在转换异常限定符（TXQ）字段中，以指示异常是在运行主机程序或主机DAT异常发生时发生的主机DAT异常 同时运行一个客人程序。 TXQ还能够指示异常与从访客页面帧实际地址或访客段帧绝对地址导出的主机虚拟地址相关联。 TXQ还能够指示较大或较小的主机帧大小优于后端客机帧。

    METHOD AND APPARATUS FOR VIRTUAL ADDRESS TRANSLATION
    245.
    发明申请
    METHOD AND APPARATUS FOR VIRTUAL ADDRESS TRANSLATION 审中-公开
    虚拟地址转换的方法和装置

    公开(公告)号：WO00002129A1

    公开(公告)日：2000-01-13

    申请号：PCT/US1999/015075

    申请日：1999-07-01

    IPC: G06F12/10

    CPC classification number: G06F12/1036

    Abstract: A method and apparatus for efficiently translating virtual to physical addresses is provided. An embodiment of the apparatus includes a TLB descriptor table that includes a series of TLB descriptors. Each TLB descriptor includes an offset that selects a TLB segment within a translation lookaside buffer (TLB). To perform a virtual to physical address translation, a processor sends a virtual address and a descriptor ID to the memory request unit. The descriptor ID is used to select the TLB segment that will be used to perform the virtual to physical address translation. Each TLB segment may have different physical and logical characteristics. In particular, each TLB segment may be associated with a different type of memory page. In this way the present invention, enables the simultaneous use of a range of page types and sizes in a single computer system.

    Abstract translation: 提供了一种有效地将虚拟地址转换为物理地址的方法和装置。 该装置的实施例包括包括一系列TLB描述符的TLB描述符表。 每个TLB描述符包括选择翻译后备缓冲器（TLB）内的TLB段的偏移量。 为了执行虚拟到物理地址转换，处理器向存储器请求单元发送虚拟地址和描述符ID。 描述符ID用于选择将用于执行虚拟到物理地址转换的TLB段。 每个TLB段可具有不同的物理和逻辑特性。 特别地，每个TLB段可以与不同类型的存储器页相关联。 以这种方式，本发明能够在单个计算机系统中同时使用一系列页面类型和大小。

    METHOD AND APPARATUS FOR PERFORMING TLB SHOOTDOWN OPERATIONS IN A MULTIPROCESSOR SYSTEM
    246.
    发明申请
    METHOD AND APPARATUS FOR PERFORMING TLB SHOOTDOWN OPERATIONS IN A MULTIPROCESSOR SYSTEM 审中-公开
    用于在多处理器系统中执行TLB SHOOTDOWN操作的方法和装置

    公开(公告)号：WO1998027493A1

    公开(公告)日：1998-06-25

    申请号：PCT/US1997021744

    申请日：1997-12-01

    Applicant: INTEL CORPORATION

    Inventor： INTEL CORPORATION ,  WU, William, S. ,  PAWLOWSKI, Stephen, S. ,  MACWILLIAMS, Peter, D.

    IPC: G06F13/14

    CPC classification number: G06F12/1036 ,  G06F2212/682

    Abstract: As shown in the figure, the translation lookaside buffer, or TLB (111, 115), shootdown operation of the present invention provides for a TLB (111, 115) flush transaction communicated between multiple processors (2) on a host bus (120). One microprocessor (2) issues a TLB (111, 115) flush request on the host bus (120). The TLB (111, 115) flush request includes a page number. The microprocessors (2) receiving the request invalidate the TLB (111, 115) entry corresponding to the page number.

    Abstract translation: 如图所示，本发明的翻转后备缓冲器或TLB（111,115）击倒操作提供在主机总线（120）上的多个处理器（2）之间传送的TLB（111,115）刷新事务， 。 一个微处理器（2）在主机总线（120）上发出一个TLB（111,115）刷新请求。 TLB（111,115）刷新请求包括页码。 接收请求的微处理器（2）使与页码对应的TLB（111,115）条目无效。

    DYNAMIC MEMORY MANAGEMENT SYSTEM AND METHOD
    247.
    发明申请
    DYNAMIC MEMORY MANAGEMENT SYSTEM AND METHOD 审中-公开
    动态记忆管理系统和方法

    公开(公告)号：WO1989000727A1

    公开(公告)日：1989-01-26

    申请号：PCT/US1988002378

    申请日：1988-07-13

    Applicant: ICON INTERNATIONAL, INC.

    Inventor： ICON INTERNATIONAL, INC. ,  STEWART, Darryl, J. ,  RORDEN, Randell, J. ,  MUHLESTEIN, Mark

    IPC: G06F09/32

    CPC classification number: G06F12/1036

    Abstract: A system and method for allowing dynamic configuration of the translation entries (134) within a memory management system (18) of a computer. In the disclosed embodiment, portions of a logical address (102) from a CPU (10) are defined as offset (104), page (106), volume/page (108) and volume fields (110). The offset field (104) is presented unaltered to a main memory (24) to select a specific location within a page of memory. The page field (106) forms a first portion of the address of a selected entry in the translation memory (136). The volume/page field (108) is combined with the contents of a base register (122) as specified by the contents of a mask register (126) to form the remaining portion of the address of a selected entry in the translation memory (136). The volume field (110) and volume/page fields (108) are compared to one or more tags (138) stored in the translation memory (136) to determine if a match exists. If a match exists, the frame pointer (140) associated with the matching tag is output to main memory as the physical address of the frame containing the desired page.

    248.
    发明专利
    未知

    公开(公告)号：NO875391A

    公开(公告)日：1988-06-24

    申请号：NO875391

    申请日：1987-12-22

    Applicant: HONEYWELL BULL

    Inventor： NUSINOV EUGENE ,  JOYCE THOMAS F

    IPC: G06F12/08 ,  G06F12/10 ,  G06F12/14 ,  G11C8/00

    CPC classification number: G06F12/145 ,  G06F12/1036 ,  Y02D10/13

    Abstract: A segment descriptor unit (SDU) includes a divided random access memory (RAM), a content addressable memory (CAM) and decoder circuits interconnected for performing dynamic and static address translation operations within a minimum of chip area and power. The CAM is arranged to store a number of entries which include segment number and validity information associated with a corresponding number of segment descriptors. The RAM contains locations allocated for storing segment descriptor words (SDW's) and working data. Each SDW is logically divided into two fields, a static translation word (STW) field containing all of the bits required for performing a static address translation operation and an access control word (ACW) field containing all of the bits required for verifying compliance with system security. The bits of each STW and ACW are stored in alternate bit positions of the SDW locations. Each pair of RAM bit locations couple to a common read/write amplifier and multiplexer circuit. Through the use of microinstruction commands coded to specify different address translation functions, the STW and ACW fields selected by the CAM are read out from RAM during different intervals for carrying out the steps of those operations.

    AUTOMATIC MEMORY MANAGEMENT USING A MEMORY MANAGEMENT UNIT
    249.
    发明申请
    AUTOMATIC MEMORY MANAGEMENT USING A MEMORY MANAGEMENT UNIT 审中-公开
    使用内存管理单元进行自动内存管理

    公开(公告)号：WO2017001305A1

    公开(公告)日：2017-01-05

    申请号：PCT/EP2016/064761

    申请日：2016-06-24

    Applicant: AICAS GMBH

    Inventor： SIEBERT, Fridtjof

    IPC: G06F12/02

    CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/10 ,  G06F12/1036 ,  G06F2212/7201 ,  G06F2212/7205

    Abstract: In a computer system (100), an automatic memory management module (150) operates by receiving from a mutator (140), memory allocation requests (141) for particular objects (O[1]...O[9]) to be stored in a random-access memory (120) and allocating particular logical addresses (Axy; A2.1... A1.4) within a logical address space (155) to the particular objects (O[1]...O[9]). The automatic memory management module (150) distinguishes the particular objects (O[1]...O[9]) according to at least one criterion and allocates logical addresses (A1.y) from a first sub-space (155-1) and logical addresses (A2.y) from a second sub-space (155-2). A memory management unit (130) maps the allocated logical addresses (A2.y) from the second sub-space (155-2) to physical memory (P1... P104) in the random-access memory (120). The logical addresses within the first sub-space (155-1) are compacted in combination with moving corresponding objects in the random-access memory.

    Abstract translation: 在计算机系统（100）中，自动存储器管理模块（150）通过从变换器（140）接收特定对象（O [1] ... O [9]）的存储器分配请求（141）来进行操作 存储在随机存取存储器（120）中并且将逻辑地址空间（155）内的特定逻辑地址（Axy; A2.1 ... A1.4）分配给特定对象（O [1] ... O [ 9]）。 自动存储器管理模块（150）根据至少一个标准区分特定对象（O [1] ... O [9]），并从第一子空间（155-1-1）分配逻辑地址（A1.y） ）和来自第二子空间（155-2）的逻辑地址（A2.y）。 存储器管理单元（130）将所分配的逻辑地址（A2.y）从第二子空间（155-2）映射到随机存取存储器（120）中的物理存储器（P1 ... P104）。 第一子空间（155-1）中的逻辑地址与随机存取存储器中移动的对应对象相结合而被压缩。

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