公开(公告)号：EP1171820A4

公开(公告)日：2005-06-15

申请号：EP00911736

申请日：2000-02-08

Applicant: YOTTA YOTTA INC

Inventor： BROWN WILLIAM P ,  MATHEWS MICHAEL B

IPC: G06F3/06 ,  G06F11/00 ,  G06F11/20 ,  H04L1/22 ,  H04L29/08 ,  G06F11/07 ,  G06F11/10 ,  G06F11/16 ,  G06F12/00 ,  G06F13/14 ,  G06F13/36 ,  G06F13/42

CPC classification number: G06F3/065 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/067 ,  G06F3/0689 ,  G06F9/526 ,  G06F11/1088 ,  G06F11/1096 ,  G06F11/2089 ,  G06F11/2094 ,  G06F11/2097 ,  G06F2201/85 ,  H04L67/1097

Abstract: Multiple Array Management Functions (80) included in controller (30) are connected to multiple redundancy groups (40) over a storage area network (SAN), such as a fiber-channel based SAN (50). The multiple Array Management Functions share management responsibility of the redundancy groups, each of which typically includes multiple resources spread over multiple disks (45). The AMFs provide concurrent access to the redundancy groups for associated host systems. When a host requests an AMF to perform an operation on a resource, the AMF synchronizes with the other AMFs sharing control of the redundancy group that includes the resource to be operated on, so as to obtain a lock on the resource. While performing the operation, the AMF send replication data and state information associated with the resource such that if the AMF fails, any of the other AMFs are able to complete the operation and maintain data reliability and coherency.

公开(公告)号：EP1115064A3

公开(公告)日：2004-12-29

申请号：EP00112906.3

申请日：2000-06-19

Applicant: Hitachi, Ltd.

Inventor： Nakayama, Shinichi, Hitachi, Ltd. Intel.Prop.Group ,  Yokohata, Shizuo, Hitachi, Ltd. Intel.Prop.Group

IPC: G06F13/38

CPC classification number: G06F11/2092 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0683 ,  G06F3/0689 ,  G06F11/2005 ,  G06F11/2007 ,  G06F13/385 ,  G06F15/16 ,  G06F2201/85 ,  Y10S707/99932 ,  Y10S707/99937 ,  Y10S707/99938

Abstract: A storage subsystem and a storage controller adapted to take advantage of high data transfer rates of fibre channels while offering enhanced reliability and availability and capable of connecting with a plurality of host computers having multiple different interfaces. A loop is provided to serve as a common loop channel having fibre channel interfaces. Host interface controllers (HIFC) connected to host computers having different interfaces permit conversion between the fibre channel interface and a different interface as needed. Control processors, shared by the host interface controllers, each reference FCAL (fibre channel arbitrated loop) management information to capture a frame having an address of the processor in question from among the frames passing through the loop. I/O processing is then carried out by the controller in accordance with a range of logical unit numbers (LUN) set in the captured frame.

公开(公告)号：EP1296246A2

公开(公告)日：2003-03-26

申请号：EP02256620.2

申请日：2002-09-24

Applicant: Sun Microsystems, Inc.

Inventor： Phelps, Andrew E ,  Drogichen, Daniel P ,  Kay, Donald B

IPC: G06F11/00 ,  H04Q3/68

CPC classification number: G06F11/2007 ,  G06F11/1423 ,  G06F11/2038 ,  G06F2201/85

Abstract: A method and apparatus are disclosed for dynamically reconfiguring a computing system. The method comprises detecting a predetermined condition triggering a reconfiguration of the computing system, and dynamically reconfiguring a signal path affected by the condition from a first mode to a second mode responsive to detecting the condition. The apparatus is a computing system, comprising: a plurality of I/O switches, a crossbar switch, a plurality of signal paths, and a system controller. Each signal path is defined by an I/O switch and the crossbar switch. The system controller is capable of detecting a predetermined condition triggering a reconfiguration, and dynamically reconfiguring at least one of the signal paths affected by the condition from a first mode to a second mode.

Abstract translation: 公开了用于动态地重新配置计算系统的方法和装置。 所述方法包括检测触发所述计算系统的重新配置的预定条件，以及响应于检测到所述条件，动态地将由所述条件影响的信号路径从第一模式重新配置到第二模式。 该装置是一种计算系统，包括：多个I / O开关，十字开关，多个信号路径和系统控制器。 每个信号路径由I / O开关和交叉开关定义。 系统控制器能够检测触发重新配置的预定条件，并且动态地重新配置受到条件影响的信号路径中的至少一个从第一模式到第二模式。

公开(公告)号：EP0747822B1

公开(公告)日：2001-10-04

申请号：EP96109061.0

申请日：1996-06-05

Applicant: Hitachi, Ltd.

Inventor： Matsumoto, Yoshiko ,  Muraoka, Kenji

IPC: G06F11/20

CPC classification number: G06F11/2092 ,  G06F3/0601 ,  G06F11/1008 ,  G06F11/3433 ,  G06F2003/0697 ,  G06F2201/85

Abstract: An external storage system has a storage unit (500) for storing data and a plurality of storage controllers (200, 400) for controlling data transfer between an upper level system (100) and the storage unit. Each storage controller has a data buffer (240, 440) for temporarily storing data and a controller (250, 450) for controlling the operation of the storage controller. The external storage system has a management memory (310) for storing management information of the plurality of storage controllers each of which accesses this memory to monitor the operation states of other storage controllers. The external storage system has a first storage controller for processing an input-output request from the upper level system and a second storage controller for standing by for backup for a failed storage controller. In accordance with load distribution information stored in the management memory, the process to be executed by the first storage controller is partially executed by the second storage controller to improve the performance of the whole external storage system.

公开(公告)号：EP0843851A2

公开(公告)日：1998-05-27

申请号：EP96925880.0

申请日：1996-07-30

Applicant: Symbios, Inc.

Inventor： DULAC, Keith, Bernard ,  PHILLIPS, Grover, George

IPC: G06F3 ,  G06F11 ,  G06F13 ,  G11B20 ,  G11B31 ,  H04N5 ,  H04N7

CPC classification number: G06F11/201 ,  G06F11/1076 ,  G06F2201/85 ,  G06F2211/1014 ,  H04N7/17336

Abstract: An apparatus includes a first bus, a second bus, and a storage module having a first and second output with the first output being connected to the first bus and a second output being connected to the second bus. A first buffer storage and a second buffer storage in which the first buffer storage is connected to the first bus and the second buffer storage is connected to the second bus. The second buffer storage includes an error correction module. First and second network adapters are connected to the first and second buses respectively. The first network adapter also includes a connection to the first buffer. A processor in the apparatus includes a first processor circuitry for transferring the data using a first path through the first output in the storage module to the first buffer storage and from the first buffer storage to the first network adapter. A second processor circuitry is for transferring data using a second path through the second output to the second buffer storage through the error correction module and from the second buffer storage to the second network adapter, wherein the second processor circuitry is responsive to an error in the storage module.

公开(公告)号：EP0681239A2

公开(公告)日：1995-11-08

申请号：EP95111006.3

申请日：1989-12-08

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Cutts, Richard W., Jr. ,  Banton, Randall G. ,  Jewett, Douglas E. ,  Norwood, Peter C. ,  Debacker, Kenneth C. ,  Mehta, Nikhil A. ,  Allison, John David ,  Horst, Robert W.

IPC: G06F11/16 ,  G06F11/18

CPC classification number: G06F9/3863 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/18 ,  G06F11/181 ,  G06F11/182 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2015 ,  G06F11/2017 ,  G06F2201/85 ,  G11C29/74

Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

Abstract translation: 该容错计算机系统使用执行相同指令流的多个（例如，三个）相同的CPU，其中多个（例如，两个）存储器模块在其CPU的地址空间中存储相同数据的重复。 CPU通过检测诸如存储器引用的事件和使其他CPU之前的任何CPU停止直到所有执行相应的功能同时被松动地同步。 中断通过确保所有CPU在其指令流中的相同点实现中断来实现同步。 通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。 使用两个相同的I / O总线实现I / O功能，每个总线单独地仅耦合到一个存储器模块。 许多I / O处理器耦合到两个I / O总线。 通过一对冗余相同的I / O处理器访问I / O设备，但只有一个被指定为主动控制给定的I / O设备。 然而，在一个I / O处理器发生故障的情况下，I / O设备可以被另一个I / O设备访问，而不需要系统关闭，即仅通过在指令控制下重新指定I / O设备的寄存器的地址。

公开(公告)号：EP0372580A3

公开(公告)日：1991-07-24

申请号：EP89122709.2

申请日：1989-12-08

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Cutts, Richard W., Jr. ,  Jewett, Douglas E. ,  Southworth, Richard A. ,  Debacker, Kenneth C. ,  Mehta, Nikhil A. ,  Allison, John David ,  Horst, Robert W.

IPC: G06F11/16 ,  G06F11/18

CPC classification number: G06F11/185 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1645 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/181 ,  G06F11/182 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2017 ,  G06F15/17 ,  G06F2201/85 ,  G11C29/74

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

公开(公告)号：EP0372579A3

公开(公告)日：1991-07-24

申请号：EP89122708.4

申请日：1989-12-08

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Cutts, Richard W., Jr. ,  Banton, Randall G. ,  Jewett, Douglas E. ,  Norwood, Peter C. ,  Debacker, Kenneth C. ,  Mehta, Nikhil A. ,  Allison, John David ,  Horst, Robert W.

IPC: G06F11/16 ,  G06F11/18

CPC classification number: G06F9/3863 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/18 ,  G06F11/181 ,  G06F11/182 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2015 ,  G06F11/2017 ,  G06F2201/85 ,  G11C29/74

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

公开(公告)号：EP0372579A2

公开(公告)日：1990-06-13

申请号：EP89122708.4

申请日：1989-12-08

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Cutts, Richard W., Jr. ,  Banton, Randall G. ,  Jewett, Douglas E. ,  Norwood, Peter C. ,  Debacker, Kenneth C. ,  Mehta, Nikhil A. ,  Allison, John David ,  Horst, Robert W.

IPC: G06F11/16 ,  G06F11/18

CPC classification number: G06F9/3863 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/18 ,  G06F11/181 ,  G06F11/182 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2015 ,  G06F11/2017 ,  G06F2201/85 ,  G11C29/74

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

Abstract translation: 容错配置中的计算机系统使用执行相同指令流的多个相同的CPU，在存储相同数据的副本的CPU的地址空间中具有多个相同的存储器模块。 多个CPU松动地同步，如通过检测诸如内存引用的事件，并阻止其他任何CPU之前的事件，直到所有同时执行该功能; 中断可以通过确保所有CPU在其指令流中的相同点实现中断来同步。 通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。 使用两个相同的I / O总线实现I / O功能，每个总线单独地仅耦合到一个存储器模块。 许多I / O处理器耦合到两个I / O总线。 I / O设备通过一对相同（冗余）I / O处理器访问，但只有一个被指定为主动控制给定的设备; 然而，在一个I / O处理器发生故障的情况下，I / O设备可以被另一个I / O设备访问，而不需要系统关闭，即仅在指令控制下重新指定I / O设备的寄存器的地址。

公开(公告)号：JP2018536941A

公开(公告)日：2018-12-13

申请号：JP2018529105

申请日：2016-12-07

Applicant: アップテイク テクノロジーズ、インコーポレイテッド

Inventor： マイケル ゴールドステイン ,  トム ラーヴェンスベルク ,  ウィル ハンスマン

IPC: G05B23/02

CPC classification number: G06F11/079 ,  G01D3/08 ,  G01M99/008 ,  G06F11/008 ,  G06F11/0709 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/0787 ,  G06F11/0793 ,  G06F11/2007 ,  G06F11/26 ,  G06F11/263 ,  G06F2201/85 ,  G06N5/02 ,  G06N5/04 ,  G06N7/005 ,  G06Q10/04 ,  G06Q10/06312 ,  G06Q10/067 ,  G06Q10/20 ,  G08B21/18 ,  H04L45/22

Abstract: 本発明は、アセット監視システムにおけるデータ入力操作を予測モデルに基づいて修正するように構成したコンピュータアーキテクチュア及びソフトウェアを提供する。本発明によれば、アセット監視システムにより、事象の群のうちの少なくとも1つの事象(例えば、障害事象)が将来の所定の期間内で所定のアセットに生じる可能性があるかどうかの指標を出力する予測モデルを実行しうるようにする。アセット監視システムは、この予測モデルの出力に基づいて、取り込んだデータに対する記憶位置と、取り込んだアセットからのデータ変数の組と、アセットからデータを取り込むレートとの何れか又はこれらの任意の組合せのような、所定のアセットからのデータを取り込むための1つ以上の操作パラメータを修正しうるようにする。