Abstract:
A method for controlling access of a processor to a resource, wherein the processor has an instruction set including a virtualization extension, may include executing a resource access instruction by the processor using the virtualization extension, whereby the resource access instruction conveys a virtual address (VA) and a virtual machine identifier. The method may also include translating the virtual address to a physical address based on the virtual machine identifier, and looking-up an access control rule table using the physical address as a search key. Each entry of the rule table includes a virtual machine identifier. The method further includes controlling access to the resource based on the output of the rule table and a match between the virtual machine identifier returned by the table and the virtual machine identifier conveyed in the resource access instruction.
Abstract:
An electronic device includes a first and a second integrated-circuit chip that are stacked at a distance from one another, and a plurality of electrical connection pillars and at least one protective barrier interposed between the chips. The protective barrier delimits a free space between mutually opposing local regions of the chips, and an encapsulation block extends around the chip that has the smaller mounting face and over the periphery of the mounting face of the other chip. The electrical connection pillars and the protective barrier are made of at least one identical metallic material with a view to simultaneous fabrication.
Abstract:
An electronic device includes a substrate plate with a traversing passage. An electronic component, mounted to the substrate plate, includes an integrated circuit chip with an optical sensor and an opaque protective plate mounted above the sensor. The electronic component is mounted with the chip facing the substrate plate such that the protective plate is engaged with the traversing passage. Electrical connection elements extend between the chip and the substrate plate. An internal block of encapsulation material extends into the traversing passage of the substrate plate between the chip and the substrate plate so as to embed the electrical connection elements.
Abstract:
A method includes separating image data into high frequency image data and low frequency image data. The high frequency image data is separated into windows, with each window containing pixels. The low frequency image data is separated into windows corresponding respectively to the plurality of windows of the high frequency image data, with each window containing pixels. For each window in the high frequency image data, a number of textured pixels in the window is determined, the textured pixels being pixels that vary greatly in luminance value with respect to other pixels in the window, and a window modification is determined such that the number of textured pixels in the window is reduced. For each corresponding window in the low frequency image data, the window modification is applied, and each textured pixel in the window is corrected based upon the other pixels in the window.
Abstract:
A substrate board includes an electrical connection network on a face thereof. An integrated-circuit chip is mounted to the face of the substrate board in electrical contact with the electrical connection network. A local reinforcing or balancing layer made of a non-metallic material is mounted to the face of the substrate board in at least one local zone free of the face which is free of metal portions of the electrical connection network.
Abstract:
An autofocus method determines that a ranging device of a digital camera has failed in an attempt to provide a distance estimation. The ranging device provides one or more parameters indicating conditions related to the failure of the ranging device to provide the distance estimation. An autofocus sequence based on the one or more parameters is then performed.
Abstract:
A method for managing an operation of an encrypted global interleaved memory space physically implemented according to an interleaving addressing scheme in encrypted memory banks of a plurality of memories respectively belonging to a plurality of channels. The method includes providing each channel with a local address pointer configured to be incrementally moved along the global memory space each time the global memory space is addressed at the current address pointed by the pointer, and in an absence of movement of the local pointer of a channel during a time period, addressing the global memory space from the channel through the address interleaving with a specific transaction at the current address, and upon reception at the channel of the specific transaction having been initiated by the channel, re-encrypting data located at the current address with a new encryption key and incrementing the local address pointer to its next position.
Abstract:
The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.
Abstract:
An image includes at least first and second digital samples corresponding to first and second different color components. The image is compressed by detecting level changes of a first signal formed of the sequence of the first samples and by detecting level changes of a second signal formed of the sequence of the second samples. A determination is made as to whether the detected changes coincide with each other. The first signal is decimated. The compressed image that is output includes the decimated first signal, the second signal and a further signal indicative of coinciding detected changes.
Abstract:
An image sensor pixel may include an array of four photosites, a transverse isolator wall separating the array in two rows of two photosites, and a longitudinal isolator wall separating the array in two columns of two photosites. Both ends of the longitudinal wall may be set back relative to the edges of the array. First and second conversion nodes may be arranged in the spaces between the longitudinal wall and the edges of the matrix. Each conversion node may be common to two adjacent photosites, and an independent transfer gate may be between each photosite and the corresponding conversion node.