公开(公告)号：US5534743A

公开(公告)日：1996-07-09

申请号：US301473

申请日：1994-09-07

Applicant: Gary W. Jones ,  Steven M. Zimmerman

Inventor： Gary W. Jones ,  Steven M. Zimmerman

IPC: G01R33/10 ,  G02B27/00 ,  G02B27/01 ,  G02B27/22 ,  G09G3/00 ,  H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J9/24 ,  H01J29/02 ,  H01J29/94 ,  H01J31/12 ,  H04N5/70 ,  H04N5/74 ,  H04N13/00 ,  H01J1/02

CPC classification number: G09G3/001 ,  G01R33/10 ,  G02B27/017 ,  G02B27/0172 ,  G02B27/0176 ,  G02B27/2235 ,  H01J1/3042 ,  H01J29/028 ,  H01J29/94 ,  H01J3/022 ,  H01J31/127 ,  H01J9/025 ,  H04N13/0422 ,  H04N13/0438 ,  H04N13/044 ,  H04N13/0459 ,  H04N13/0497 ,  H04N5/7408 ,  G02B2027/0132 ,  G02B2027/0136 ,  H01J2201/304 ,  H01J2201/30426 ,  H01J2201/30457 ,  H01J2201/319 ,  H01J2209/385 ,  H01J2329/00 ,  H01J2329/8625 ,  H01J2329/863 ,  H01J2329/864 ,  H04N13/0059 ,  H04N13/0285 ,  H04N13/0427 ,  H04N13/0456 ,  H04N5/70 ,  H04N5/7491

Abstract: A field emitter structure, comprising: a base substrate; a field emitter element on the base substrate; a multilayer differentially etched dielectric stack circumscribingly surrounding the field emitter element on the base substrate; and a gate electrode overlying the multilayer differentially etched dielectric stack, and in circumscribing spaced relationship to the field emitter element. Also disclosed are electron source devices, comprising an electron emitter element including a material selected from the group consisting of leaky dielectric materials, and leaky insulator materials, as well as electron source devices, comprising an electron emitter element including an insulator material doped with a tunneling electron emission enhancingly effective amount of a dopant species, and thin film triode devices.

Abstract translation: 一种场发射器结构，包括：基底; 基底基板上的场发射体元件; 围绕基底衬底上的场发射体元件的多层差分蚀刻介质堆叠; 以及覆盖多层差分蚀刻的电介质叠层的栅电极，并且以与外界发射极元件间隔开的关系。 还公开了电子源器件，其包括电子发射器元件，其包括选自由漏电介质材料和漏绝缘体材料组成的组的材料，以及电子源器件，其包括电子发射器元件，该电子发射器元件包括掺杂有隧道 电子发射增加有效量的掺杂物种类和薄膜三极管器件。

公开(公告)号：US5522751A

公开(公告)日：1996-06-04

申请号：US483670

申请日：1995-06-07

Applicant: Robert H. Taylor ,  Jules D. Levine

Inventor： Robert H. Taylor ,  Jules D. Levine

IPC: H01J31/12 ,  H01J1/30 ,  H01J1/304 ,  H01J9/02 ,  H01J9/18

CPC classification number: H01J1/3042 ,  H01J2201/319

Abstract: The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90. Also disclosed is an arrangement of emitter clusters comprising conductive plates 102 having a plurality of microtip emitters 104 formed thereon, or spaced thereform by a thin layer of resistive material, each cluster adjacent and laterally spaced from a stripe conductor 100 by a region 106 of a resistive material. The conductive stripes 100 are substantially parallel to each other, are spaced from one another by two conductive plates 102, and are joined by bus regions 110 outside the active area of the display.

Abstract translation: 场发射平板显示装置的发射极板60包括电阻材料层68和导电材料的网状结构62。 在由导体62的网格限定的间隔内，还在电阻涂层68的顶部形成导电板78.导电板78的上表面上形成了示意为锥体形状的微尖头发射体70。 通过它们与导电板78的电连接，所有微尖端发射器70将处于相等的电位。在一个实施例中，单个导电板82位于导体80的每个网格间隔内; 在另一个实施例中，四个导电板92对称地定位在导体90的每个网格间隔内。还公开了发射器​​簇的布置，其包括导电板102，其具有形成在其上的多个微尖端发射器104，或者由薄层 材料，每个簇通过电阻材料的区域106与条状导体100相邻和横向间隔开。 导电条100基本上彼此平行，通过两个导电板102彼此隔开，并且通过显示器的有效区域外的总线区域110连接。

公开(公告)号：US5455196A

公开(公告)日：1995-10-03

申请号：US214926

申请日：1994-03-17

Applicant: Gary A. Frazier

Inventor： Gary A. Frazier

IPC: H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J31/20 ,  H01L21/465

CPC classification number: H01J29/04 ,  H01J1/3042 ,  H01J31/203 ,  H01J9/025 ,  H01J2201/319 ,  Y10S148/172

Abstract: A method of forming an array of electron field emitters at a face of a semiconductor layer is disclosed. The method includes the steps of: providing a semiconductor workpiece having a plurality of field emitter sites on a face thereof; for each site, forming a conductive column having a base coupled to the site and an upstanding end opposed to the base; for each conductive column, forming a metallic column on the upstanding end of the conductive column; depositing an electrically conductive polymer layer over the workpiece; etching the electrically conductive polymer layer to selectively expose the metallic columns; placing the workpiece in an electrolytic etchant solution capable of etching the metallic columns; applying an electric potential between the conductive polymer layer and an anode electrode in the etchant to etch the metallic columns into a respective plurality of sharp emitter tips; and removing the conductive polymer layer. Where the metallic column is tungsten, an aqueous solution of potassium hydroxide is disclosed as an etchant. Where the metallic column is a platinum-iridium alloy, an aqueous solution of calcium chloride and hydrochloric acid is disclosed as an etchant.

Abstract translation: 公开了一种在半导体层的表面形成电子场发射体阵列的方法。 该方法包括以下步骤：提供在其表面上具有多个场发射器位置的半导体工件; 形成一个导电柱，该导电柱具有连接到该位置的底座和一个与底座相对的直立端; 对于每个导电柱，在导电柱的直立端上形成金属柱; 在工件上沉积导电聚合物层; 蚀刻导电聚合物层以选择性地暴露金属柱; 将工件放置在能够蚀刻金属柱的电解蚀刻溶液中; 在蚀刻剂中的导电聚合物层和阳极电极之间施加电势，以将金属柱蚀刻成相应的多个尖锐的发射极尖端; 并除去导电聚合物层。 当金属柱是钨时，公开了氢氧化钾的水溶液作为蚀刻剂。 当金属柱是铂 - 铱合金时，公开了氯化钙和盐酸的水溶液作为蚀刻剂。

公开(公告)号：US5396150A

公开(公告)日：1995-03-07

申请号：US84484

申请日：1993-07-01

Applicant: Biing-Seng Wu ,  Jammy C.-M. Huang

Inventor： Biing-Seng Wu ,  Jammy C.-M. Huang

IPC: H01J3/02 ,  H01J9/02 ,  H01J1/30

CPC classification number: H01J3/022 ,  H01J9/025 ,  H01J2201/319 ,  H01J2329/00

Abstract: A high resolution matrix addressed flat panel display having single field emission microtip redundancy is formed. A dielectric base substrate is provided. Parallel, spaced conductors acting as cathode columns for the display are formed upon the substrate. A layer of insulation is located over the cathode columns. Parallel, spaced conductors acting as gate lines for the display is formed over the layer of insulation at a right angle to the cathode columns. The intersections of the cathode columns and gate lines are the pixels of the display. A plurality of openings at the pixels extend through the insulating layer and gate lines. At each of the pixels are a plurality of field emission microtips connected to and extending up from the cathode conductor columns and into the plurality of openings. There is a circular resistive layer surrounding each of the field emission microtips to obtain emission uniformity by sustaining the cathode to gate voltage.

Abstract translation: 形成具有单场发射微尖头冗余的高分辨率矩阵寻址平板显示器。 提供介电基底基板。 作为显示器的阴极柱的平行，间隔的导体形成在基板上。 绝缘层位于阴极柱之上。 作为显示器的栅极线的平行的隔开的导体以与阴极柱成直角的绝缘层形成。 阴极柱和栅极线的交点是显示器的像素。 像素处的多个开口延伸穿过绝缘层和栅极线。 在每个像素处是连接到阴极导体柱并且向上延伸到多个开口中的多个场发射微尖端。 围绕每个场发射微尖端的圆形电阻层通过将阴极维持在栅极电压来获得发射均匀性。

公开(公告)号：US5382185A

公开(公告)日：1995-01-17

申请号：US40944

申请日：1993-03-31

Applicant: Henry F. Gray ,  David S. Y. Hsu

Inventor： Henry F. Gray ,  David S. Y. Hsu

IPC: H01J1/304 ,  H01J9/02 ,  H01J1/30

CPC classification number: H01J9/025 ,  H01J1/3042 ,  H01J2201/30423 ,  H01J2201/319

Abstract: Thin-film edge field emitter devices are provided which are capable of low voltage operation. The method of manufacture of the devices takes advantage of chemical beam deposition and other thin-film fabrication techniques. Both gated and ungated devices are provided and all of the devices include a plurality of thin-films deposited on the side-wall of a non-flat substrate. The gated emitter devices include alternating conductive and electrically insulating layers, and upper parts of the latter are removed to expose the upper edges of the conductive layers, with a central one of these conductive layers comprising an emitter for emitting electrons. The emitter devices can be inexpensively produced with a high degree of precision and reproducibility without the need for expensive lithographic machines. The devices can be used in field emitter arrays employed as vacuum transistors, vacuum microelectronic analog and digital devices, and modulated or cold electron sources.

Abstract translation: 提供能够进行低电压操作的薄膜边缘场发射极器件。 该装置的制造方法利用化学束沉积和其它薄膜制造技术。 提供了门控和非门装置，并且所有装置都包括沉积在非平板基板的侧壁上的多个薄膜。 门控发射极器件包括交替的导电和电绝缘层，并且去除其上部，以暴露导电层的上边缘，这些导电层中的一个包括用于发射电子的发射极。 发射极器件可以以高精度和重现性廉价地生产，而不需要昂贵的光刻机。 这些器件可用于作为真空晶体管的真空发射极阵列，真空微电子模拟和数字器件以及调制或冷电子源。

公开(公告)号：US5372973A

公开(公告)日：1994-12-13

申请号：US53794

申请日：1993-04-27

Applicant: Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

Inventor： Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

IPC: H01J1/304 ,  H01J9/02 ,  H01L21/3105 ,  H01L21/465

CPC classification number: H01J9/025 ,  H01L21/31053 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2209/0226

Abstract: A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.

Abstract translation: 用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积 具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii） 化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料 。

公开(公告)号：US5371431A

公开(公告)日：1994-12-06

申请号：US846281

申请日：1992-03-04

Applicant: Gary W. Jones ,  Ching-Tzong Sune

Inventor： Gary W. Jones ,  Ching-Tzong Sune

IPC: H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J29/87 ,  H01J31/12 ,  H01J1/30

CPC classification number: H01J3/021 ,  H01J1/3042 ,  H01J9/025 ,  H01J2201/319

Abstract: A vertical microelectronic field emitter includes a conductive top portion and a resistive bottom portion in an elongated column which extends vertically from a horizontal substrate. An emitter electrode may be formed at the base of the column, and an extraction electrode may be formed adjacent the top of the column. The elongated column reduces the parasitic capacitance of the microelectronic field emitter to provide high speed operation, while providing uniform column-to-column resistance. The field emitter may be formed by first forming tips on the face of a substrate and then forming trenches in the substrate around the tips to form columns in the substrate, with the tips lying on top of the columns. The trenches are filled with a dielectric and a conductor layer is formed on the dielectric. Alternatively, trenches may be formed in the face of the substrate with the trenches defining columns in the substrate. Then, tips are formed on top of the columns. The trenches are filled with dielectric and the conductor layer is formed on the dielectric to form the extraction electrodes.

Abstract translation: 垂直微电子场发射器包括从水平衬底垂直延伸的细长柱中的导电顶部部分和电阻底部部分。 发射电极可以形成在柱的底部，并且可以在柱的顶部附近形成引出电极。 细长柱减小微电子场发射器的寄生电容，以提供高速操作，同时提供均匀的柱对列电阻。 场发射器可以通过在衬底的表面上首先形成尖端然后在衬底周围形成尖端的沟槽形成衬底中的柱，其中尖端位于柱的顶部。 沟槽填充有电介质，并且在电介质上形成导体层。 或者，可以在衬底的表面形成沟槽，其中沟槽限定在衬底中的列。 然后，尖端形成在列的顶部。 沟槽用电介质填充，并且导体层形成在电介质上以形成提取电极。

公开(公告)号：US5318918A

公开(公告)日：1994-06-07

申请号：US814960

申请日：1991-12-31

Applicant: Gary A. Frazier

Inventor： Gary A. Frazier

IPC: H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J31/20 ,  H01L21/335 ,  H01L21/283

CPC classification number: H01J29/04 ,  H01J1/3042 ,  H01J31/203 ,  H01J9/025 ,  H01J2201/319 ,  Y10S148/172

Abstract: This is a method of forming an array of electron emitters at the face of a semiconductor layer. The method comprises the steps of depositing a layer of polycrystalline silicon on a face of a semiconductor workpiece; doping the polycrystalline silicon layer to render the polycrystalline silicon layer conductive; and for each of a plurality of emitter cells, performing an orientation-dependent polycrystalline silicon etch to define a pyramid for the cell having a base affixed to the workpiece and an upstanding tip opposed to the base. Preferably the method also includes the steps of forming a field effect transistor at the face of the workpiece prior to the depositing of the layer, with the pyramid having a base in conductive contact with the drain of the transistor. The polycrystalline silicon layer may be doped in situ after deposition.

Abstract translation: 这是在半导体层的表面形成电子发射体阵列的方法。 该方法包括以下步骤：在半导体工件的表面上沉积多晶硅层; 掺杂多晶硅层以使多晶硅层导电; 并且对于多个发射极单元中的每一个，执行取向相关多晶硅蚀刻以限定用于具有固定到工件的基部的单元和与基座相对的直立尖端的金字塔。 优选地，该方法还包括以下步骤：在沉积层之前在工件的表面处形成场效应晶体管，金字塔具有与晶体管的漏极导电接触的基极。 多晶硅层可以沉积后原位掺杂。

公开(公告)号：US5312777A

公开(公告)日：1994-05-17

申请号：US951283

申请日：1992-09-25

Applicant: John E. Cronin ,  Kent E. Morrett ,  Michael D. Potter ,  Matthew J. Rutten

Inventor： John E. Cronin ,  Kent E. Morrett ,  Michael D. Potter ,  Matthew J. Rutten

IPC: H01J9/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/44

CPC classification number: H01L27/10852 ,  H01J9/025 ,  H01L27/108 ,  H01J2201/319

Abstract: Bidirectional field emission devices (FEDs) and associated fabrication methods are described. A basic device includes a first unitary field emission structure and an adjacently positioned, second unitary field emission structure. The first unitary structure has a first cathode portion and a first anode portion, while the second unitary structure has a second cathode portion and a second anode portion. The structures are positioned such that the first cathode portion opposes the second anode portion so that electrons may flow by field emission thereto and the second cathode portion opposes the first anode portion, again so that electrons may flow by field emission thereto. A control mechanism defines whether the device is active, while biasing voltages applied to the first and second unitary structures define the direction of current flow. Multiple applications exist for such a bidirectional FED. For example, an FED DRAM cell is discussed, as are methods for fabricating the various devices.

Abstract translation: 描述了双向场致发射器件（FED）和相关的制造方法。 基本装置包括第一单一场发射结构和相邻定位的第二单一场致发射结构。 第一单一结构具有第一阴极部分和第一阳极部分，而第二整体结构具有第二阴极部分和第二阳极部分。 结构被定位成使得第一阴极部分与第二阳极部分相对，使得电子可以通过场发射流动，并且第二阴极部分与第一阳极部分相反，使得电子可以通过场发射而流动。 控制机构定义设备是否有效，而施加到第一和第二单一结构的偏置电压限定电流的方向。 存在这种双向FED的多种应用。 例如，讨论了FED DRAM单元，以及用于制造各种器件的方法。

公开(公告)号：US5229682A

公开(公告)日：1993-07-20

申请号：US841194

申请日：1992-02-21

Applicant: Hiroshi Komatsu

Inventor： Hiroshi Komatsu

IPC: H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01L23/544

CPC classification number: H01J3/022 ,  H01J1/3042 ,  H01J9/025 ,  H01L23/544 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2209/0226 ,  H01L2223/54473 ,  H01L2924/0002

Abstract: A field emission device and method for manufacturing which comprises using a diffusion mask to preserve an area of a silicon substrate for use as a cathode while all around the cathode the substrate is being diffused with oxygen to form an insulating layer. And further comprising depositing a molybdenum gate electrode layer on the insulating layer and etching the molybdenum gate electrode layer such that the diffusion mask falls off and the insulating layer is dissolved around the cathode through the hole formed in the gate electrode layer by the diffusion mask being removed. The gate electrode openings are therefore automatically and independently self-aligned with their respective cathodes.

Abstract translation: 一种场致发射器件及其制造方法，其包括使用扩散掩模来保留用于阴极的硅衬底的面积，同时所述衬底周围的所述衬底全部被氧扩散以形成绝缘层。 并且还包括在所述绝缘层上沉积钼栅极层并蚀刻所述钼栅极层，使得所述扩散掩模脱落，并且所述绝缘层通过所述扩散掩模通过形成在所述栅电极层中的所述孔溶解在所述阴极周围 删除。 因此，栅电极开口自动且独立地与它们各自的阴极自对准。