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    Direct digitally tunable microwave oscillators and filters
    251.
    发明授权
    Direct digitally tunable microwave oscillators and filters 有权

    公开(公告)号：US07259417B2

    公开(公告)日：2007-08-21

    申请号：US10269593

    申请日：2002-10-10

    Applicant: Eliezer Pasternak

    Inventor： Eliezer Pasternak

    IPC: H01L29/76

    CPC classification number: H04B1/18 ,  H03B2201/0208 ,  H03B2201/025

    Abstract: A tunable element in the microwave frequency range is described that may include one or more tunable elements that are directly digitally controlled by a digital bus connecting a digital control circuit to each controlled element. In particular, each digital signal is filtered by a digital isolation technique so that the signal reaches the tunable elements with very low noise. The low noise digital signals are then converted to analog control voltages. The direct D/A conversion is accomplished by a special D/A converter which is manufactured as an integral part of a substrate. This D/A converter in accordance with the invention may consist of a resistor ladder or a directly digitally controlled capacitor. The direct digitally controlled capacitor may be a cantilevered type capacitor having multiple separate electrodes or sub-plates representing binary bits that may be used to control the capacitor. A low cost microwave oscillator is disclosed in which some of the filters and oscillators are direct digitally tuned elements.

    APPARATUS AND METHOD FOR PHASE LOCK LOOP GAIN CONTROL
    252.
    发明申请
    APPARATUS AND METHOD FOR PHASE LOCK LOOP GAIN CONTROL 有权
    相位锁定增益控制的装置和方法

    公开(公告)号：US20070018747A1

    公开(公告)日：2007-01-25

    申请号：US11534870

    申请日：2006-09-25

    Applicant: Ramon Gomez

    Inventor： Ramon Gomez

    IPC: H03L5/00

    CPC classification number: H03L7/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1278 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/025 ,  H03D7/165 ,  H03D7/18 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

    Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL, control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.

    Abstract translation: 增益补偿器补偿锁相环（PLL）中变容二极管调谐电压调谐振荡器（VCO）的增益变化。 VCO包括具有多个固定电容器的并联LC电路，其可以根据电容器控制信号切换或切换出LC电路，以执行VCO的频带选择调谐。 增益补偿器通过产生基于控制LC电路中的固定电容器的相同电容器控制信号的电荷泵参考电流来补偿可变VCO增益。 增益补偿器通过使用单位电流源复制参考刻度电流来产生电荷泵参考电流。 参考比例电流复制的次数是基于切换到LC电路的固定电容，因此是PLL的频带。 参考比例电流是基于一个PLL来控制的，该控制指定了某些PLL特性，例如参考频率，环路带宽和环路阻尼。 因此，除了补偿可变VCO增益之外，参考泵电流可以有效地优化用于改变PLL工作条件。

    Discrete clock generator and timing/frequency reference
    255.
    发明申请
    Discrete clock generator and timing/frequency reference 有权
    离散时钟发生器和定时/频率参考

    公开(公告)号：US20060158268A1

    公开(公告)日：2006-07-20

    申请号：US11384973

    申请日：2006-03-20

    Applicant: Michael McCorquodale ,  Scott Pernia ,  Sundus Kubba ,  Justin O'Day ,  Gordon Carichner

    Inventor： Michael McCorquodale ,  Scott Pernia ,  Sundus Kubba ,  Justin O'Day ,  Gordon Carichner

    IPC: H03L7/00

    CPC classification number: G06F1/04 ,  G06F1/08 ,  H03B5/06 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/124 ,  H03B2201/025 ,  H03J1/0008 ,  H03J2200/10 ,  H03L1/00 ,  H03L1/02 ,  H03L1/022 ,  H03L1/025 ,  H03L3/00 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/099 ,  H03L7/183 ,  H03L2207/50

    Abstract: In various embodiments, the invention provides a discrete clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

    Abstract translation: 在各种实施例中，本发明提供使用LC振荡器拓扑的离散时钟发生器和/或定时和频率参考，其具有频率控制器来控制和提供稳定的谐振频率，然后可以将其提供给其它第二电路，例如 作为处理器或控制器。 提供了频率稳定性，如选择的参数（如温度和制造工艺变化）的变化。 各种装置实施例包括适于响应于多个参数的至少一个参数提供信号的传感器; 以及频率控制器，其适于响应于所述第二信号来修改所述谐振频率。 在示例性实施例中，响应于温度波动将传感器实现为电流源，并且频率控制器被实现为可选择地耦合到谐振器或一个或多个控制电压的多个受控电抗模块。 受控电抗模块可以包括固定或可变电容或电感，并且可以是二进制加权的。 还提供了电阻模块的阵列，以产生一个或多个控制电压。

    Quadrature voltage controlled oscillators with phase shift detector
    256.
    发明授权
    Quadrature voltage controlled oscillators with phase shift detector 有权
    具有相移检测器的正交电压控制振荡器

    公开(公告)号：US07075377B2

    公开(公告)日：2006-07-11

    申请号：US10864969

    申请日：2004-06-10

    Applicant: Emmanuel Metaxakis

    Inventor： Emmanuel Metaxakis

    IPC: H03B5/12

    CPC classification number: H03L7/00 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/124 ,  H03B27/00 ,  H03B2201/025 ,  H03J2200/10

    Abstract: In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated ‘I’ and ‘Q’ channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.

    Abstract translation: 在无线应用中，使用产生能够彼此正交振荡的信号的正交振荡器。 正交振荡器由两个差分改进的Colpitts振荡器组成。 电容器组允许从多个离散的可能频率中选择期望的频率。 正交振荡器还与在所产生的“I”和“Q”通道的使用点处连接的相位误差检测器耦合，并且通过电流源的控制提供校正装置以确保在点处的相移 - 使用保持在所需的九十度。

    High frequency semiconductor integrated circuit and radio communication system
    258.
    发明授权
    High frequency semiconductor integrated circuit and radio communication system 失效
    高频半导体集成电路和无线电通信系统

    公开(公告)号：US07020444B2

    公开(公告)日：2006-03-28

    申请号：US10372922

    申请日：2003-02-26

    Applicant: Jiro Shinbo ,  Hirotaka Oosawa ,  Noriyuki Kurakami ,  Masumi Kasahara ,  Robert Astle Henshaw

    Inventor： Jiro Shinbo ,  Hirotaka Oosawa ,  Noriyuki Kurakami ,  Masumi Kasahara ,  Robert Astle Henshaw

    IPC: H04B1/40

    CPC classification number: H03L7/10 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/025 ,  H03D3/008 ,  H03J1/005 ,  H03J2200/10 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/193

    Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit for the transmission PLL circuit is configured to be operable in a plurality of bands. The communication semiconductor integrated circuit also comprises a circuit for measuring the oscillating frequency of the oscillator circuit for the transmission PLL circuit, and a storage circuit for storing the result of measurement made by the measuring circuit. A band to be used by the oscillator circuit for the transmission PLL circuit is determined based on values for setting the oscillating frequencies of the oscillator circuit forming part of the reception PLL circuit and the intermediate frequency oscillator circuit, and the result of measurement stored in the storage circuit.

    Abstract translation: 通信半导体集成电路具有形成在单个半导体芯片上的传输PLL电路的一部分的振荡器电路以及形成接收PLL电路的一部分的振荡器电路和用于中频的振荡器电路。 用于传输PLL电路的振荡器电路被配置为可在多个频带中操作。 通信半导体集成电路还包括用于测量用于传输PLL电路的振荡器电路的振荡频率的电路和用于存储由测量电路进行的测量结果的存储电路。 用于传输PLL电路的振荡电路使用的频带基于用于设置构成接收PLL电路和中频振荡器电路的一部分的振荡电路的振荡频率的值和存储在传输PLL电路中的测量结果的值来确定 存储电路。

    Capacitor bank and voltage controlled oscillator having the same
    259.
    发明申请
    Capacitor bank and voltage controlled oscillator having the same 有权
    电容器组和压控振荡器具有相同的功能

    公开(公告)号：US20050184812A1

    公开(公告)日：2005-08-25

    申请号：US11061801

    申请日：2005-02-18

    Applicant: Je-Kwang Cho

    Inventor： Je-Kwang Cho

    IPC: H03B1/00 ,  H03B5/12 ,  H03L7/00

    CPC classification number: H03B5/1215 ,  H03B5/1228 ,  H03B2201/025 ,  H03J2200/10

    Abstract: A capacitor bank includes a first node, a second node, first blocking capacitors, N first AMOS varactors, second blocking capacitors and N second AMOS varactors. The first blocking capacitors have first terminals connected to the first node and second terminals where a bias voltage is applied. The N first AMOS varactors have first terminals connected to the second terminals of the first block capacitors. The second blocking capacitors have first terminals connected to the second node and second terminals where the bias voltage is applied. The N second AMOS varactors have first terminals connected to the second terminals of the second blocking capacitors and second terminals connected to second terminals of the first AMOS varactors, respectively, wherein N binary coded signals are applied to the respective second terminals of the first AMOS varactors and the second AMOS varactors. Therefore, phase-noise degradation caused by the FM modulation may be avoided.

    Abstract translation: 电容器组包括第一节点，第二节点，第一阻塞电容器，N个第一AMOS变容二极管，第二阻塞电容器和N个第二AMOS变容二极管。 第一隔离电容器具有连接到第一节点的第一端子和施加偏置电压的第二端子。 N个第一AMOS变容二极管具有连接到第一块电容器的第二端子的第一端子。 第二隔离电容器具有连接到第二节点的第一端子和施加偏置电压的第二端子。 N个第二AMOS变容二极管分别具有连接到第二隔离电容器的第二端子的第一端子和分别连接到第一AMOS变容二极管的第二端子的第二端子，其中N个二进制编码信号被施加到第一AMOS变容二极管的相应的第二端子 和第二个AMOS变容二极管。 因此，可以避免由FM调制引起的相位噪声劣化。

    Highly stable integrated time reference
    260.
    发明申请
    Highly stable integrated time reference 有权
    高度稳定的综合时间参考

    公开(公告)号：US20050168294A1

    公开(公告)日：2005-08-04

    申请号：US11069368

    申请日：2005-03-01

    Applicant: Mike Kappes ,  Terje Gloerstad

    Inventor： Mike Kappes ,  Terje Gloerstad

    IPC: H03B1/00 ,  H03K3/0231 ,  H03L7/00

    CPC classification number: H03L7/00 ,  H03B2201/0208 ,  H03B2201/025 ,  H03K3/0231

    Abstract: An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

    Abstract translation: 可用作时钟的集成振荡器包括围绕RC时间常数振荡的电路，RC时间常数可调，以提供期望的振荡频率。 更具体地说，振荡器包括电容器阵列，其具有并联耦合的多个电容器，其中每个电容器可被选择性地包括在RC时间常数中或者选择性地被包括在其中。 不是将电容值设置为期望的电容值，而是用于调整时间常数的系统包括用于测量输出频率并将其与经认证的频率源进行比较的电路，其中通过从电容器阵列中添加或去除电容器来调整时间常数 直到内部时钟的频率与预期频率相匹配。

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