公开(公告)号：US20210273082A1

公开(公告)日：2021-09-02

申请号：US17175758

申请日：2021-02-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Edoardo BREZZA ,  A;exos GAUTHIER ,  Fabien DEPRAT ,  Pascal CHEVALIER

IPC: H01L29/737 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417

Abstract: A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.

公开(公告)号：US20210257507A1

公开(公告)日：2021-08-19

申请号：US17308651

申请日：2021-05-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles BAUDOT ,  Sebastien CREMER ,  Nathalie VULLIET ,  Denis PELLISSIER-TANON

IPC: H01L31/105 ,  H01L31/0232 ,  G02B6/12 ,  H01L31/028

Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.

公开(公告)号：US20210242087A1

公开(公告)日：2021-08-05

申请号：US17160598

申请日：2021-01-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean JIMENEZ MARTINEZ

IPC: H01L21/8228 ,  H01L27/082

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

公开(公告)号：US11043591B2

公开(公告)日：2021-06-22

申请号：US16437067

申请日：2019-06-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Gros-Jean ,  Julien Ferrand

IPC: H01L29/78 ,  H01L27/07 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

Abstract: A ferroelectric field effect transistor includes a semiconductor substrate, with first and second source/drain regions being formed within the semiconductor substrate and being separated by a channel region. An interface layer is disposed on the channel region. A gate insulator layer is disposed on the interface layer. A ferroelectric layer is disposed on the gate insulator layer.

公开(公告)号：US20210172791A1

公开(公告)日：2021-06-10

申请号：US17116851

申请日：2020-12-09

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Olivier LE NEEL ,  Stephane MONFRAY

IPC: G01J1/04 ,  H01L27/144 ,  G02B5/20 ,  G01J1/44

Abstract: A light sensor includes a first pixel and a second pixel. Each pixel has a photoconversion area. A band-stop Fano resonance filter is arranged over the first pixel. The second pixel includes no Fano resonance filter. Signals output from the first and second pixels are processed to determine information representative of the quantity of light received by the light sensor during an illumination phase in a rejection band of the band-stop Fano resonance filter.

公开(公告)号：US11031433B2

公开(公告)日：2021-06-08

申请号：US16270989

申请日：2019-02-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Lalanne ,  Laurent Gay ,  Pascal Fonteneau ,  Yann Henrion ,  Francois Guyader

IPC: H01L27/146 ,  H01L21/02 ,  H01L21/306

Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.

公开(公告)号：US20210151600A1

公开(公告)日：2021-05-20

申请号：US17095003

申请日：2020-11-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean JIMENEZ MARTINEZ

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L29/73

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

公开(公告)号：US10998431B2

公开(公告)日：2021-05-04

申请号：US16571532

申请日：2019-09-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Alexis Gauthier

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/732 ,  H01L29/10 ,  H01L29/06 ,  H01L29/165

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

公开(公告)号：US10914896B2

公开(公告)日：2021-02-09

申请号：US16199845

申请日：2018-11-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Michit ,  Patrick Le Maitre

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42 ,  G02B6/34 ,  G02B6/293 ,  H04Q11/00 ,  G02B6/35

Abstract: An elementary photonic interconnect switch is integrated into an optoelectronic chip and includes four simple photonic interconnect switches. Each simple photonic interconnect switch has two optical waveguides that cross and are linked by a ring resonator having one ring. A basic photonic interconnect switch, a complex photonic interconnect switch and/or a photonic interconnect network are integrated into an optoelectronic chip and including at least two elementary photonic interconnect switches.

公开(公告)号：US20210018815A1

公开(公告)日：2021-01-21

申请号：US16931090

申请日：2020-07-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frédéric Boeuf ,  Cyrille Barrera

IPC: G02F1/225 ,  G02F1/025 ,  G02F1/035

Abstract: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.