公开(公告)号：US20010030530A1

公开(公告)日：2001-10-18

申请号：US09826299

申请日：2001-04-04

Applicant: STMicroelectronics S.A.

Inventor： Nicolas Marty

IPC: G05F001/40

CPC classification number: G05F1/565 ,  G05F1/575

Abstract: A voltage regulator includes a regulation MOS transistor and an amplifier providing an output for driving a gate of the regulation MOS transistor. The amplifier drives the gate based upon a difference between a reference voltage and a feedback voltage. The voltage regulator may further include a circuit for making the amplifier switch to a standby mode with low current consumption when the difference between the supply voltage and the output voltage of the regulator is below a first threshold. This is done while maintaining, at the gate of the regulation transistor, a voltage that keeps the regulation transistor on. The present invention is particularly applicable to the management of power supplies in portable telephones.

Abstract translation: 电压调节器包括调节MOS晶体管和提供用于驱动调节MOS晶体管的栅极的输出的放大器。 放大器基于参考电压和反馈电压之间的差异驱动门。 电压调节器还可以包括用于当电源电压和调节器的输出电压之间的差低于第一阈值时使放大器开关进入具有低电流消耗的待机模式的电路。 这是在保持调节晶体管的栅极处保持调节晶体管导通的电压的同时完成的。 本发明特别适用于便携式电话中的电源的管理。

公开(公告)号：US20010028260A1

公开(公告)日：2001-10-11

申请号：US09795055

申请日：2001-02-26

Applicant: STMicroelectronics S.A.

Inventor： Christophe Garnier

IPC: H03K005/22

CPC classification number: H03K5/2481

Abstract: The device for the comparison of the levels of two input signals MI, PI includes a first comparator COMP1, the switching of the comparator being expressed by a change-over of the output OUT1 of the comparator from a first logic state into a second logic state, the change-over of the output OUT1 from one logic state null0null into the other state null1null being faster than the change-over in the other direction. The device also includes a second comparator COMP2 with an identical structure, to whose input the signals to be compared are applied invertedly so that the switching operations in the comparators are inverted. The output of each comparator is applied to an associated logic circuit 1, 2 capable of accelerating the inverse switching in the other comparator for a change in the output corresponding to the fastest change-over.

Abstract translation: 用于比较两个输入信号MI，PI的电平的装置包括第一比较器COMP1，比较器的切换由比较器的输出端OUT1从第一逻辑状态转换成第二逻辑状态 输出OUT1从一个逻辑状态“0”转换到另一状态“1”的转换比另一方向的转换快。 该装置还包括具有相同结构的第二比较器COMP2，与其输入相反的信号被反相地施加以使比较器中的开关操作反转。 每个比较器的输出被施加到相关联的逻辑电路1,2，其能够加速另一比较器中的反向切换，以对应于最快转换的输出变化。

公开(公告)号：US20010020857A1

公开(公告)日：2001-09-13

申请号：US09771364

申请日：2001-01-26

Applicant: STMicroelectronics S.A.

Inventor： Alexandre Malherbe ,  Fabrice Marinet ,  Alain Pomet

IPC: H03K005/01

CPC classification number: G06K19/07 ,  G06F13/426

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

Abstract translation: 用于从外部串行总线再生时钟信号的装置包括环形振荡器和计数器。 环形振荡器提供时钟信号的n个相位。 在这n个阶段中，使用一个相作为参考，并将其应用于计数器。 因此，可以对从总线接收的第一脉冲和第二脉冲之间的整个参考时钟信号周期的数量进行计数。 在接收到第二脉冲时读取振荡器中的相位状态，确定与基准时钟信号和总线的第二脉冲之间的相位延迟相对应的电流相位。 通过使用还包括环形振荡器和计数器的再生装置，可以高精度地重新生成总线的时钟信号。

公开(公告)号：US20010005618A1

公开(公告)日：2001-06-28

申请号：US09738870

申请日：2000-12-15

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Malgorzata Jurczak ,  Didier Dutartre

IPC: H01L021/00 ,  H01L021/84 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76262 ,  H01L29/0673 ,  H01L29/0676

Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

Abstract translation: 用于在隔离衬底上制造由单晶硅制成的纳米线网络的工艺包括制备包含限定主体中心部分的侧向隔离的硅体的衬底。 在具有由电介质材料制成的底壁的中心部分形成凹部，由电介质材料制成的第一对相对的平行侧壁和第二对相对的平行侧壁。 第二对的相对的平行侧壁中的至少一个由单晶硅形成。 该方法还包括从由凹槽的单晶硅制成的侧壁，由单晶SiGe合金和单晶硅制成的平行线的交替网络的凹槽中的外延生长。 此外，由单晶SiGe合金制成的线被蚀刻以在凹槽中形成由彼此绝缘的单晶硅硅制成的平行线的网络。

公开(公告)号：US10680630B1

公开(公告)日：2020-06-09

申请号：US16439038

申请日：2019-06-12

Applicant: STMicroelectronics S.A.

Inventor： Olivier David

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/08

Abstract: An interleaved analog to digital converter (“ADC”) includes a first ADC having an input for sampling an analog signal during a first time period, an output for providing a digital signal, and a power supply terminal for receiving a first power supply voltage, a second ADC having an input for sampling the analog signal during a second time period, an output for providing a digital signal, and a power supply terminal for receiving a second power supply voltage, a first skew estimator for estimating a skew value of the first ADC, a second skew estimator for estimating a skew value of the second ADC, and a comparator for comparing the skew values, adjusting the first power supply voltage in response to a first output value of the comparator, and adjusting the second power supply voltage in response to a second output value of the comparator.

公开(公告)号：US09704967B2

公开(公告)日：2017-07-11

申请号：US14853719

申请日：2015-09-14

Applicant: STMicroelectronics S.A.

Inventor： Pascal Chevalier ,  Didier Celi ,  Jean-Pierre Blanc ,  Alain Chantre

IPC: H01L29/66 ,  H01L21/82 ,  H01L29/737 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66325 ,  H01L29/737 ,  H01L29/7378

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

公开(公告)号：US09582675B2

公开(公告)日：2017-02-28

申请号：US14871873

申请日：2015-09-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Albert Martinez ,  William Orlando

IPC: G06F21/62 ,  G06F12/14 ,  G06F21/52 ,  G06F21/79 ,  G06F21/60

CPC classification number: G06F21/62 ,  G06F12/1408 ,  G06F12/1483 ,  G06F21/52 ,  G06F21/602 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2105

Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

Abstract translation: 一种用于将包含在至少第一存储器中的程序加载到执行单元可访问的第二存储器中的方法，其中程序处于第一存储器中的加密形式，用于控制对第二存储器的访问的电路是 由程序初始化数据，程序的指令，以及至少初始化数据被解密以在电路配置之后被传送到第二存储器中。

公开(公告)号：US09368611B2

公开(公告)日：2016-06-14

申请号：US13853111

申请日：2013-03-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS S.A.

Inventor： Philippe Galy ,  Patrice Dehan ,  Boris Heitz ,  Jean Jimenez

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/07

CPC classification number: H01L29/78 ,  H01L27/0727 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66643 ,  H01L29/7839

Abstract: An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.

Abstract translation: 集成电路可以包括具有S形响应的至少一个MOS晶体管。 至少一个MOS晶体管可以包括栅极区域的任一侧上的衬底，源极区域，漏极区域，栅极区域和绝缘间隔区域。 衬底可以包括位于绝缘间隔区之间的栅极区域下方的第一区域。 源极和漏极区域中的至少一个可以通过位于绝缘间隔区域下方的衬底的第二区域与衬底的第一区域分离，绝缘间隔区域可以具有与衬底的第一区域相同类型的导电性。

公开(公告)号：US09299668B2

公开(公告)日：2016-03-29

申请号：US13705503

申请日：2012-12-05

Applicant: STMicroelectronics S.A.

Inventor： Johan Bourgeat ,  Philippe Galy

IPC: H02H9/00 ,  H01L23/60 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/60 ,  H01L27/0262 ,  H01L27/0274 ,  H01L27/0296 ,  H01L29/0692 ,  H01L29/747 ,  H01L2924/0002 ,  H02H9/04 ,  H01L2924/00

Abstract: A device for protecting a set of N nodes from electrostatic discharges, wherein N is greater than or equal to three, includes a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal. Each unit includes at least one MOS transistor including a parasitic transistor connected between a pair of the N nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.

Abstract translation: 用于保护一组N个节点免受静电放电的装置，其中N大于或等于3，包括分别具有分别连接到N个节点的N个第一终端的N个单元的集合和连接在一起的N个第二终端以形成公共 终奌站。 每个单元包括至少一个MOS晶体管，其包括连接在一对N个节点之间的寄生晶体管，并且在所述一对节点之间存在电流脉冲的情况下，配置为至少临时地以包括MOS- 在亚阈值模式下工作和双极晶体管的工作。

公开(公告)号：US09236407B2

公开(公告)日：2016-01-12

申请号：US14144168

申请日：2013-12-30

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： François Roy ,  Yvon Cazaux

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14656

Abstract: An image sensor arranged inside and on top of a semiconductor substrate, having a plurality of pixels, each including: a photosensitive area, a read area, and a storage area extending between the photosensitive area and the read area; at least one first insulated vertical electrode extending in the substrate between the photosensitive area and the storage area; and at least one second insulated vertical electrode extending in the substrate between the storage area and the read area.

Abstract translation: 布置在半导体衬底的内部和顶部的具有多个像素的图像传感器，每个像素包括：感光区域，读取区域和在感光区域和读取区域之间延伸的存储区域; 至少一个第一绝缘垂直电极，其在所述基板中在所述光敏区域和所述存储区域之间延伸; 以及在所述存储区域和所述读取区域之间的所述衬底中延伸的至少一个第二绝缘垂直电极。