公开(公告)号：JP2013062469A

公开(公告)日：2013-04-04

申请号：JP2011201597

申请日：2011-09-15

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： SEO SU-KYOM

IPC: H01L23/32 ,  H01L21/60 ,  H01L23/12 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3511 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a flip-chip carrier capable of suppressing solder material bridge and package warpage that occur in a conventional MPS-C2 semiconductor package, and to provide a semiconductor packaging method using the same.SOLUTION: A flip-chip carrier 100 includes a substrate 110 and a plurality of independent pad masks 120. The substrate 110 has an upper surface 111, and a plurality of pads 112 installed on the upper surface 111. The independent pad masks 120 cover the pads 112. Each independent pad mask 120 has a photosensitive adhesive layer 121 to be adhered to the corresponding pad 112, and a light-transmissive pick and place element 122 formed on the photosensitive adhesive layer 121.

Abstract translation: 要解决的问题：提供一种能够抑制常规MPS-C2半导体封装中发生的焊料材料桥接和封装翘曲的倒装芯片载体，并提供使用其的半导体封装方法。 解决方案：倒装芯片载体100包括衬底110和多个独立焊盘掩模120.衬底110具有上表面111和安装在上表面111上的多个焊盘112.独立焊盘掩模 120覆盖焊盘112.每个独立的焊盘掩模120具有粘附到相应焊盘112的光敏粘合剂层121和形成在感光粘合层121上的透光拾取和放置元件122.权利要求（ C）2013，JPO＆INPIT

公开(公告)号：JP2011086879A

公开(公告)日：2011-04-28

申请号：JP2009240624

申请日：2009-10-19

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： HSU HUNG-HSIN ,  HSU JUI-CHING

IPC: H01L21/60

CPC classification number: H01L2224/1403 ,  H01L2224/14051

Abstract: PROBLEM TO BE SOLVED: To provide a flip chip structure of a semiconductor which has a soldered pillar-shaped bump at a surface joining device.
SOLUTION: The flip chip structure of a semiconductor includes a substrate 210, a chip 220, and a first solder 230 and additional solder 240. On the substrate 210, first connecting pads 211 and additional pads 212 are located, and the first connecting pads 211 are arranged on a first arranged line, and along it, the first connecting pad width and the first connecting pad pitch are defined. The first connecting pad pitch is longer than the first connecting pad width. On the chip 220, a group of first pillar-shaped bumps 221 which extrude on the same surface older-jointed to a group of the first connecting pads 211 through a group of the first solders 230 and a group of additional bumps 222 which are solder-jointed to a group of the additional pads 212 through a group of the additional solders 240.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供在表面接合装置处具有焊接的柱状凸起的半导体的倒装芯片结构。 解决方案：半导体的倒装芯片结构包括基板210，芯片220和第一焊料230以及附加焊料240.在基板210上，第一连接焊盘211和附加焊盘212被定位，并且第一 连接焊盘211布置在第一布置的线上，并且沿着其布置了第一连接焊盘宽度和第一连接焊盘间距。 第一连接焊盘间距长于第一连接焊盘宽度。 在芯片220上，一组第一柱状凸块221，其通过一组第一焊料230与一组第一连接焊盘211在一个较旧接合的同一表面上挤出，一组附加的焊料222是焊料 通过一组额外的焊料240与一组附加焊盘212相连。版权所有：（C）2011，JPO＆INPIT

公开(公告)号：JP2010016328A

公开(公告)日：2010-01-21

申请号：JP2008241084

申请日：2008-09-19

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： CHOU WU YI

IPC: H01L21/52

CPC classification number: H01L21/67132 ,  H01L21/6838 ,  Y10T29/53191

Abstract: PROBLEM TO BE SOLVED: To provide a die sucking module capable of preventing occurrence of a die overlap phenomenon by pulling two dies originally stuck to each other apart from each other, and achieving a high yield of a die sticking process. SOLUTION: This die sucking module 10 includes a holder 12, a sucking head 14 arranged in a bottom part of the holder and used to suck a die, and two pressing structures 16 and 16' respectively arranged in the bottom part of the holder, located on both sides of the sucking head, and stopping dies adjacent to each other by pressing heads 22 when the sucking head sucks the die, and an elastic element 24 arranged between the pressing head and the holder. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够通过将彼此原来彼此粘附的两个模具相互牵引来防止发生模具重叠现象的模具吸取模块，并且实现了模具粘贴过程的高产量。 解决方案：该模具吸入模块10包括保持器12，设置在保持器的底部并用于吸取模具的吸头14，以及分别布置在模具的底部的两个按压结构16和16' 位于吸头的两侧的支架，以及当吸头吸取模具时通过按压头22相邻的止动模以及布置在按压头和保持器之间的弹性元件24。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010016325A

公开(公告)日：2010-01-21

申请号：JP2008209234

申请日：2008-08-15

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： FANG LI-CHIH

IPC: H01L23/12 ,  H01L23/00

CPC classification number: H01L21/67126 ,  H01L23/544 ,  H01L24/26 ,  H01L24/83 ,  H01L24/97 ,  H01L2223/54486 ,  H01L2224/78 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2224/83

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package method using a panel substrate, and to provide its equipment for the electronic package method. SOLUTION: The panel substrate 101 is mounted to a working susceptor 10 to execute various package processes. Various packaging devices are disposed near the working susceptor, and moved to a working area by a mechanical arm, thus solving problems of the transportation and the warpage of substrates. In the package processes, the panel substrate is utilized, and an identical or different package process can be executed simultaneously in different regions of the panel substrate, thus increasing a yield effectively, and reducing cost. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用面板基板的电子封装方法，并提供其用于电子封装方法的设备。 解决方案：面板基板101安装到工作基座10上以执行各种封装处理。 各种包装装置设置在工作基座附近，并通过机械臂移动到工作区域，从而解决了基板的输送和翘曲的问题。 在封装工艺中，利用面板基板，并且可以在面板基板的不同区域中同时执行相同或不同的封装工艺，从而有效地提高产量并降低成本。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009290186A

公开(公告)日：2009-12-10

申请号：JP2008240088

申请日：2008-09-18

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： CHEN CHIN-TI

IPC: H01L23/12

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L2224/73203

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating semiconductor elements, which directly adhere a wafer and electrically connect it on a substrate thereby singulation processing is simultaneously performed for the wafer and substrate to reduce a time for fabricating the semiconductor elements.
SOLUTION: The method for fabricating semiconductor elements includes the step of providing a substrate having wiring on the upper surface thereon, the step of electrically connecting the substrate on the wafer to output or input a signal, the step of adhering gel between the wafer and substrate to fix the wafer and substrate, and the step of singulating the substrate and wafer and separating them to form a plurality of semiconductor elements.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种制造半导体元件的方法，其直接粘附晶片并将其电连接到基板上，从而对晶片和基板同时执行单晶化处理，以减少制造半导体元件的时间。 解决方案：制造半导体元件的方法包括提供在其上表面上具有布线的基板的步骤，将晶片上的基板电连接以输出或输入信号的步骤，将凝胶粘附在 晶片和衬底以固定晶片和衬底，以及分离衬底和晶片并分离它们以形成多个半导体元件的步骤。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009130343A

公开(公告)日：2009-06-11

申请号：JP2007307415

申请日：2007-11-28

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FANG LI-CHIH ,  FAN WEN-JENG

IPC: H01L23/12

CPC classification number: H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/83192 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a chip mounting process that saves testing time of memory chip packages and also reduce total production time. SOLUTION: The chip mounting process includes the steps of: forming a chip group on a unit substrate of a substrate strip; making a plurality of circumscribing pads on the bonding surface of each unit substrate; electrically connecting the chip group to a corresponding unit substrate; sealing the chip group in a sealed body on the substrate strip; and carrying out a PMC step to cure the sealed body and burn in test and high temperature test at the same time. A plurality of probe terminals of burn-in probe plate are electrically connected to the circumscribing pads. The substrate strip has a plurality of wiring removal regions and the circumscribing pads of different unit substrates are electrically isolated before the PMC step. In the last stage, the package is diced to isolate unit substrates equipped with the sealed chip group and the circumscribing pads into unit packages. With this process, testing time of memory chip packages and total production time can be largely reduced. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供芯片安装过程，节省存储芯片封装的测试时间，并减少总生产时间。 解决方案：芯片安装工艺包括以下步骤：在衬底条的单元衬底上形成芯片组; 在每个单元基板的接合表面上制造多个外接垫; 将芯片组电连接到相应的单元基板; 将芯片组密封在衬底条上的密封体中; 并进行PMC步骤，固化密封体并同时在试验和高温试验中燃烧。 老化探针板的多个探针端子电连接到外接垫。 衬底条具有多个布线移除区域，并且在PMC步骤之前，不同单元基板的外接垫被电隔离。 在最后阶段，将包装件切割成将装有密封芯片组和外接垫的单元基板隔离成单元包装。 通过这个过程，可以大大减少内存芯片封装的测试时间和总生产时间。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008277720A

公开(公告)日：2008-11-13

申请号：JP2007170255

申请日：2007-06-28

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： FANG LI-CHIH ,  IWATA TAKAO ,  FAN WEN-JENG

IPC: H01L23/12 ,  H01L21/60

CPC classification number: H05K3/3452 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor chip package substrate and its solder pad structure. SOLUTION: The semiconductor chip package substrate includes a core layer 30, an electrically conductive structure 32 installed on the surface of the core layer, and an insulating layer 34 that coats the electrically conductive structure and has at least one patterning opening 36. The patterning opening has a center part 361 and a plurality of wing parts 362 that extend outwardly from the edge of the center part and defines an exposure region with an electrically conductive structure into a solder pad 38. Because of a design having a center region and a plurality of wing face regions of the solder pad, the adhesion effect between the solder pad and a solder ball is increased. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供半导体芯片封装基板及其焊盘结构。 解决方案：半导体芯片封装基板包括芯层30，安装在芯层表面上的导电结构32和涂覆导电结构并具有至少一个图案化开口36的绝缘层34。 图形化开口具有中心部分361和从中心部分的边缘向外延伸的多个翼部分362，并且将具有导电结构的曝光区域限定为焊盘38.由于具有中心区域和 焊盘的多个翼面区域，焊料焊盘和焊球之间的粘合效应增加。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008258521A

公开(公告)日：2008-10-23

申请号：JP2007101475

申请日：2007-04-09

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： HSU HUNG-HSIN ,  WU CHIH-WEI

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a multi-chip lamination substrate, a multi-chip lamination mounting structure using the same, and an application of the same in which each chip group can independently operate.
SOLUTION: A multi-chip lamination substrate 200 at least has a first wire bonding finger 211, a second wire bonding finger 212, a trace, and a loop wiring. The first wire bonding finger 211 and the second wire bonding finger 212 are adjacent to a die attaching area. The loop wiring is connected in series to the first wire bonding finger 211 and the second wire bonding finger 212, and also connected to the trace. A multi-chip lamination mounting structure includes the substrate 200, a first chip 50 provided in the die attaching area, and a second chip 60 laminated on the first chip 50.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种多芯片层叠基板，使用该多芯片层叠基板的多芯片层叠安装结构及其各芯片组可独立操作的应用。 解决方案：多芯片层压基板200至少具有第一引线接合指211，第二引线接合指212，迹线和环路布线。 第一引线接合指211和第二引线接合指212与管芯附接区相邻。 环路布线与第一引线接合指211和第二引线接合指212串联连接，并且还连接到迹线。 多芯片层叠安装结构包括基板200，设置在管芯安装区域中的第一芯片50和层压在第一芯片50上的第二芯片60.版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008053612A

公开(公告)日：2008-03-06

申请号：JP2006230533

申请日：2006-08-28

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L23/28 ,  H01L21/56 ,  H01L23/12

CPC classification number: H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an MAP semiconductor package in which MAP packaging air bubbles are not generated. SOLUTION: The semiconductor package comprises a chip carrier 210, at least one chip 220, and a seal 230. The chip carrier 210 has an upper surface 211, a lower surface 212, and a plurality of partitioning edges 213 between the upper surface 211 and the lower surface 212. The chip 220 is arranged on the chip carrier 210 and connected electrically therewith. The seal 230 seals the chip 220 hermetically while covering the upper surface 211 of the chip carrier 210, and mold fluidity limiting portions 231 are formed on the opposite sides of the seal 230. The mold fluidity limiting portions 231 are lower than the central top surface 233 of the seal 230 and aligned with the partitioning edges 213 of the corresponding chip carrier 210. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供不生成MAP包装气泡的MAP半导体封装。 解决方案：半导体封装包括芯片载体210，至少一个芯片220和密封件230.芯片载体210具有上表面211，下表面212和在上部表面之间的多个分隔边缘213 表面211和下表面212.芯片220布置在芯片载体210上并与其电连接。 密封件230密封芯片220，同时覆盖芯片载体210的上表面211，并且模制流动性限制部分231形成在密封件230的相对侧上。模具流动性限制部分231低于中心顶部表面 233，并与对应的芯片载体210的分隔边缘213对准。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP3122586U

公开(公告)日：2006-06-15

申请号：JP2006002607

申请日：2006-04-07

Applicant: 力成科技股▲ふん▼有限公司Powertech Technology Inc.

Inventor： 嘉鍮 洪 ,  政賢 邱

IPC: H01L23/50 ,  H01L21/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012

Abstract: 【課題】積層チップパッケージ構造を提供する。
【解決手段】積層チップパッケージ構造は、リードフレームと、第一チップと、第二チップと、電気的接続素子と、成形材料と、からなる。 リードフレームは、複数の支承脚と複数のリードからなる。 第一チップは、第一接合素子によりリードフレームの一側に配置され、支承脚を部分的に覆蓋し、これらの支承脚は、第一チップ周縁から第一チップに延伸し、第一チップの支承となる。 第二チップは、第二接合素子により、リードフレームの第一チップの反対側に配置され、支承脚を部分的に覆蓋し、第一チップ、第二チップ、及び、一部が覆蓋された支承脚は、共同で開放式の型流れトレンチを定義する。 電気的接続素子は、リードにより第一、第二チップに電気的に接続される。 成形材料は、第一、第二チップ、電気的接続素子、及び、一部のリードフレームを被覆し、成形材料は型流れトレンチに流れて、第一、第二チップ、及び、一部の支承脚を充分に覆蓋する。 支承脚は、ダイパッドの代わりとなり、成形工程時の好ましい型流れが得られ、高い信頼度を得る。
【選択図】図４B