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公开(公告)号：US20250125279A1
公开(公告)日：2025-04-17
申请号：US18485523
申请日：2023-10-12
Applicant: STMicroelectronics International N.V.
Inventor： Kai Quan CHENG , Tat Ming TEO , Andrew John PRICE , William HALLIDAY , Bhagya Prakash BANDUSENA , Calum RITCHIE
IPC: H01L23/552 , H01L23/00
Abstract: An example apparatus and optical emission device for preventing the transmission of electromagnetic radiation to and from targeted electrical components of an electronic device are provided. The example apparatus may include an optical emissions component electrically connected to a target electrical portion and configured to generate an optical output. The example apparatus may further include a wire bond electromagnetic interference cage configured to block the passage of electromagnetic emissions. The wire bond electromagnetic interference cage may include a plurality of bond wires, wherein each bond wire is electrically coupled to an electrical ground, and wherein the wire bond electromagnetic interference cage overlays at least a portion of the target electrical portion. In addition, the wire bond electromagnetic interference cage may further define an electromagnetic interference cage opening through which the optical output passes.
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公开(公告)号：US20250125232A1
公开(公告)日：2025-04-17
申请号：US18910748
申请日：2024-10-09
Applicant: STMicroelectronics International N.V.
Inventor： Brunella CAFRA , Antonio LANDI , Agata GRASSO , Crocifisso Marco Antonio RENNA
IPC: H01L23/495
Abstract: Wettable metalization multilayer formed by an adhesion layer, containing titanium; a barrier layer, containing nickel; and a sintering layer, containing silver. A portion of the sintering layer, facing the barrier layer, contains atoms of a metal material chosen between aluminum and tin. A portion of the barrier layer facing the sintering layer may contain atoms of the metal material. The sintering layer is obtained depositing by PVD and spinning a metal material layer and then a silver layer, causing the diffusion of the atoms of the metal material in the silver layer.
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公开(公告)号：US20250125228A1
公开(公告)日：2025-04-17
申请号：US18910661
申请日：2024-10-09
Applicant: STMicroelectronics International N.V.
Inventor： Guendalina CATALANO , Alessandro MELLINA GOTTARDO , Alberto ARRIGONI
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31
Abstract: A semiconductor die is arranged at a die mounting region at a first surface of a die pad in a substrate. The die pad has a second surface opposite the first surface. Laser beam energy is applied to the second surface of the die pad to form in the second surface of the die pad a recessed peripheral portion surrounding a central portion opposite the die mounting region at the first surface. An encapsulation of electrically insulating material is molded onto the substrate. During molding, the electrically insulating material covers the recessed peripheral portion and leakage of the electrically insulating material over the central portion is countered in response to the peripheral portion of the second surface of the die pad being recessed.
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公开(公告)号：US20250119129A1
公开(公告)日：2025-04-10
申请号：US18830200
申请日：2024-09-10
Applicant: STMicroelectronics International N.V.
Inventor： Stephane Razafimandimby
Abstract: The present description relates to an electronic circuit comprising a first circuit configured to generate, based on a first periodic analog signal, a plurality of second signals having offset voltage levels, a second circuit configured to generate third periodic digital signals according to respective crossings, by the second signals, of at least one threshold, and a third circuit configured to determine an amplitude range in which the first periodic analog signal is located, according to a number of the third periodic digital signals.
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公开(公告)号：US20250117499A1
公开(公告)日：2025-04-10
申请号：US18483278
申请日：2023-10-09
Applicant: STMicroelectronics International N.V.
Inventor： Michael PEETERS
Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses for data encryption.
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Patent Agency Ranking
公开(公告)号：US20250112565A1
公开(公告)日：2025-04-03
申请号：US18375005
申请日：2023-09-29
Applicant: STMicroelectronics International N.V.
Inventor： Harsha ADEMANE , Rosario ATTANASIO , Dino COSTANZO
Abstract: Systems, apparatuses, and methods to perform startup step detection in an internal permanent magnet synchronous machine are provided. Startup step detection may providing a motor comprising a rotor and stator, wherein the rotor may be positioned in one of six rotor step positions. The startup step detection may include determining which of the six rotor step positions the rotor is in. This may be performed by determining, prior to starting the motor, a sequence of voltage signals while taking current measurements for each voltage signal. The current measurements may be a change in current over time. Of the current measurements a largest maximum current measurement may be determined, which may be used to identify the current rotor step position.
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27.发明申请公开(公告)号：US20250112556A1
公开(公告)日：2025-04-03
申请号：US18904313
申请日：2024-10-02
Applicant: STMicroelectronics International N.V.
Inventor： Alessandro BERTOLINI , Alessandro GASPARINI
Abstract: A non-inverting buck boost DC-DC converter operates with a ripple-hysteretic-current-mode-control including: a first state where control signals close a first high side switch and a second low side switch; a second state where control signals close the first high side switch and a second high side switch; a third state where control signals close a first low side switch and the second high side switch; and a fourth state where control signals close the first low side switch and the second low side switch. Control signal peak voltage and valley voltage are detected. Passing between the first, second, third and fourth states is dependent on peak voltage detection, valley voltage detection, expiration of a variable first time interval following entering the second state, and expiration of a fixed second time interval following entering the third state.
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公开(公告)号：US20250112107A1
公开(公告)日：2025-04-03
申请号：US18890514
申请日：2024-09-19
Applicant: STMicroelectronics International N.V.
Inventor： Roseanne DUCA
IPC: H01L23/367 , H01L21/48
Abstract: At least one package includes a die including a first surface, a second surface opposite to the first surface, and one or more sidewalls transverse to the first surface and the second surface. The one or more sidewalls extend from the first surface to the second surface. A plurality of separate and distinct heat sinks is on the first surface of the die. Each respective separate and distinct heat sink of the plurality of separate and distinct heat sinks is separate and distinct from adjacent separate and distinct heat sinks of the plurality of separate and distinct heat sinks. A plurality of channels separates each respective heat sink of the plurality of heat sinks from adjacent heat sinks of the plurality of heat sinks. In some packages, an elastic thermally conductive material is present within and fills the plurality of channels.
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公开(公告)号：US12267190B2
公开(公告)日：2025-04-01
申请号：US18644590
申请日：2024-04-24
Applicant: STMicroelectronics International N.V.
Inventor： Iztok Bratuz , Vinko Kunc , Maksimiljan Stiglic
IPC: H04L25/49
Abstract: Various embodiments of the present disclosure disclose decoding techniques for mitigating data corruption due to duty cycle distortion, jitter, and other distortions to a digital signal. Decoding processes, apparatuses, and systems are provided that utilize a decoding framework for improving the accuracy of output bit streams generated from digital signals. An example process receives data indicative of a digital signal, generates a signal measurement for the digital signal that includes signal length descriptive between a two rising edges of a digital signal or two falling edges of the demodulated digital signal, and generates at least one portion of an output bit stream for the digital signal based at least in part on the signal measurement.
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公开(公告)号：US12265124B1
公开(公告)日：2025-04-01
申请号：US18474511
申请日：2023-09-26
Applicant: STMicroelectronics International N.V.
Inventor： Sandeep Jain , Akshay Kumar Jain , Jeena Mary George
IPC: G01R31/319 , G01R31/317 , G01R31/3193
Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N−1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N−1 number of redundant flip-flops is observed through the functional path to determine faults.
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